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| m68hc08 microcontrollers freescale.com 68hc908mr24 advance information rev. 4.1 mc68hc908mr24/d august 1, 2005
mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor list of sections 3 advance information ? mc68hc908mr24 list of sections section 1. general description . . . . . . . . . . . . . . . . . . . . 29 section 2. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . 39 section 3. random-a ccess memory (ram) . . . . . . . . . . 55 section 4. flash memory . . . . . . . . . . . . . . . . . . . . . . . . 57 section 5. configuration register (config) . . . . . . . . . 69 section 6. central processor unit (cpu) . . . . . . . . . . . . 73 section 7. system integration mo dule (sim) . . . . . . . . . 91 section 8. clock generator modu le (cgm) . . . . . . . . . . 109 section 9. pulse-width modulator for motor control (pwmmc) . . . . . . . . . . . . . . . . . . 135 section 10. monitor rom (mon) . . . . . . . . . . . . . . . . . . 191 section 11. timer interface a (tim a). . . . . . . . . . . . . . . 203 section 12. timer interface b (tim b). . . . . . . . . . . . . . . 231 section 13. serial pe ripheral interface module (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 section 14. serial comm unications interface module (sci) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 section 15. input/output (i/o) port s . . . . . . . . . . . . . . . 321 section 16. computer operatin g properly (cop) . . . . 337 section 17. external interrupt (irq ) . . . . . . . . . . . . . . . 343 section 18. low-voltage inhibit (lvi) . . . . . . . . . . . . . . 349 section 19. analog-to-digital converter (adc) . . . . . . 355 section 20. power-on re set (por) . . . . . . . . . . . . . . . . 371 advance information mc68hc908mr24 ? rev. 4.1 4 list of sections freescale semiconductor list of sections section 21. electrical sp ecifications. . . . . . . . . . . . . . . 373 section 22. mechanical specificati ons . . . . . . . . . . . . . 385 section 23. ordering in formation . . . . . . . . . . . . . . . . . 389 glossary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor table of contents 5 advance information ? mc68hc908mr24 table of contents section 1. general description 1.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.4 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.5 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.5.1 power supply pins (v dd and v ss ) . . . . . . . . . . . . . . . . . . . . 35 1.5.2 oscillator pins (osc1 and osc2) . . . . . . . . . . . . . . . . . . . . 35 1.5.3 external reset pin (rst ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 1.5.4 external interrupt pin (irq ) . . . . . . . . . . . . . . . . . . . . . . . . . 36 1.5.5 cgm power supply pins (v dda and v ssa ) . . . . . . . . . . . . . 36 1.5.6 external filter capac itor pin (cgmxfc) . . . . . . . . . . . . . . . 36 1.5.7 analog power supply pins (v ddad and v ssad ). . . . . . . . . . 36 1.5.8 adc voltage decoup ling capacitor pin (v refh ) . . . . . . . . . 36 1.5.9 adc voltage reference low pin (v refl ) . . . . . . . . . . . . . . 37 1.5.10 port a input/output (i/o) pins (pta7?pta0) . . . . . . . . . . . . 37 1.5.11 port b i/o pins (ptb7/atd7?ptb 0/atd0) . . . . . . . . . . . . . 37 1.5.12 port c i/o pins (ptc6?ptc2 and ptc1/atd9?ptc0/atd8) . . . . . . . . . . . . . . . . . . . . . . . 37 1.5.13 port d input-only pins (ptd6/is3 ?ptd4/is1 and ptd3/fault4?ptd0/fault1) . . . . . . . . . . . . . . . . 37 1.5.14 pwm pins (pwm6?pwm1) . . . . . . . . . . . . . . . . . . . . . . . . . 38 1.5.15 pwm ground pin (pwmgn d) . . . . . . . . . . . . . . . . . . . . . . . 38 1.5.16 port e i/o pins (pte7/tch3a?pte3/tclka and pte2/tch1b?pte0/tclkb). . . . . . . . . . . . . . . . . . 38 1.5.17 port f i/o pins (ptf5/txd?ptf4/rxd and ptf3/miso?ptf0/ spsck) . . . . . . . . . . . . . . . . . . . 38 advance information mc68hc908mr24 ? rev. 4.1 6 table of contents freescale semiconductor table of contents section 2. memory map 2.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.3 unimplemented memory loc ations . . . . . . . . . . . . . . . . . . . . . 39 2.4 reserved memory locations . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.5 i/o section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.6 monitor rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 section 3. random-access memory (ram) 3.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 section 4. flash memory 4.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 4.4 flash control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.5 flash charge pump frequ ency control . . . . . . . . . . . . . . . . 60 4.6 flash erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.7 flash program/margin r ead operation . . . . . . . . . . . . . . . . . 62 4.8 flash block protecti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.9 flash block protect regist er . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.10 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table of contents mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor table of contents 7 section 5. configurat ion register (config) 5.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 section 6. central pr ocessor unit (cpu) 6.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.4 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.4.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.4.2 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.4.3 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.4.4 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.4.5 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.5 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.6 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.7 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 section 7. system integration module (sim) 7.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.3 sim bus clock control and generation . . . . . . . . . . . . . . . . . . 94 7.3.1 bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 7.3.2 clock startup from po r or lvi reset . . . . . . . . . . . . . . . . . 94 7.3.3 clocks in wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 7.4 reset and system initializa tion. . . . . . . . . . . . . . . . . . . . . . . . . 95 7.4.1 external pin reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.4.2 active resets from inte rnal sources . . . . . . . . . . . . . . . . . . 97 advance information mc68hc908mr24 ? rev. 4.1 8 table of contents freescale semiconductor table of contents 7.4.2.1 power-on reset (por) . . . . . . . . . . . . . . . . . . . . . . . . . . 98 7.4.2.2 computer operati ng properly (cop) reset. . . . . . . . . . . 99 7.4.2.3 illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 7.4.2.4 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 7.4.2.5 low-voltage inhibit (lvi) reset . . . . . . . . . . . . . . . . . . . 100 7.5 sim counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 7.5.1 sim counter during power-on rese t . . . . . . . . . . . . . . . . 100 7.5.2 sim counter and reset states. . . . . . . . . . . . . . . . . . . . . . 100 7.6 exception control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 7.6.1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 7.6.1.1 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 7.6.1.2 software interrupt (swi) instruction. . . . . . . . . . . . . . . . 104 7.6.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 7.7 low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 7.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 7.7.2 sim reset status regist er . . . . . . . . . . . . . . . . . . . . . . . . 107 section 8. clock generator module (cgm) 8.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 8.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 8.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 8.4.1 crystal oscillator circ uit . . . . . . . . . . . . . . . . . . . . . . . . . . .111 8.4.2 phase-locked loop circ uit (pll) . . . . . . . . . . . . . . . . . . . 113 8.4.2.1 pll circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 8.4.2.2 acquisition and tracking modes . . . . . . . . . . . . . . . . . . 115 8.4.2.3 manual and automatic pll b andwidth modes . . . . . . . 115 8.4.2.4 programming the pll . . . . . . . . . . . . . . . . . . . . . . . . . . 117 8.4.2.5 special programming exceptions . . . . . . . . . . . . . . . . . 119 8.4.3 base clock selector ci rcuit . . . . . . . . . . . . . . . . . . . . . . . . 119 8.4.4 cgm external connectio ns . . . . . . . . . . . . . . . . . . . . . . . . 120 table of contents mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor table of contents 9 8.5 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 8.5.1 crystal amplifier input pin (osc1). . . . . . . . . . . . . . . . . . . 121 8.5.2 crystal amplifier ou tput pin (osc2) . . . . . . . . . . . . . . . . . 121 8.5.3 external filter capacitor pin (c gmxfc) . . . . . . . . . . . . . . 122 8.5.4 pll analog power pin (v dda ) . . . . . . . . . . . . . . . . . . . . . . 122 8.5.5 oscillator enable signal (simoscen). . . . . . . . . . . . . . . . 122 8.5.6 crystal output frequency signal (cgmxclk) . . . . . . . . . 122 8.5.7 cgm base clock output (cgmout) . . . . . . . . . . . . . . . . . 122 8.5.8 cgm cpu interrupt (cgmint) . . . . . . . . . . . . . . . . . . . . . 123 8.6 cgm registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 8.6.1 pll control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 8.6.2 pll bandwidth control register . . . . . . . . . . . . . . . . . . . . 126 8.6.3 pll programming regist er . . . . . . . . . . . . . . . . . . . . . . . . 128 8.7 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 8.8 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 8.9 acquisition/lock time spec ifications . . . . . . . . . . . . . . . . . . . 130 8.9.1 acquisition/lock time definitions. . . . . . . . . . . . . . . . . . . .130 8.9.2 parametric influences on reaction time . . . . . . . . . . . . . . 132 8.9.3 choosing a filter capac itor . . . . . . . . . . . . . . . . . . . . . . . . 133 8.9.4 reaction time calculat ion . . . . . . . . . . . . . . . . . . . . . . . . . 133 section 9. pulse-width mo dulator for motor control (pwmmc) 9.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 9.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 9.4 timebase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 9.4.1 resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 9.4.2 prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 9.5 pwm generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 9.5.1 load operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143 9.5.2 pwm data overflow and underf low conditions. . . . . . . . . 148 advance information mc68hc908mr24 ? rev. 4.1 10 table of contents freescale semiconductor table of contents 9.6 output control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 9.6.1 selecting six independe nt pwms or three complementary pwm pairs . . . . . . . . . . . . . . . . . . . . . 148 9.6.2 dead-time insertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 9.6.3 top/bottom correction with motor phase current polarity sensing . . . . . . . . . . . . . . . . . . . . . . . . 154 9.6.4 output polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 9.6.5 pwm output port contro l. . . . . . . . . . . . . . . . . . . . . . . . . . 160 9.7 fault protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 9.7.1 fault condition input pi ns . . . . . . . . . . . . . . . . . . . . . . . . . 166 9.7.1.1 fault pin filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 9.7.1.2 automatic mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 9.7.1.3 manual mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 9.7.2 software output disable . . . . . . . . . . . . . . . . . . . . . . . . . . 170 9.7.3 output port control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170 9.8 initialization and the pwm en bit . . . . . . . . . . . . . . . . . . . . . . 171 9.9 pwm operation in wait mode . . . . . . . . . . . . . . . . . . . . . . . . 172 9.10 control logic block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 9.10.1 pwm counter registers. . . . . . . . . . . . . . . . . . . . . . . . . . .173 9.10.2 pwm counter modulo registers . . . . . . . . . . . . . . . . . . . . 174 9.10.3 pwm x value registers. . . . . . . . . . . . . . . . . . . . . . . . . . .175 9.10.4 pwm control register 1. . . . . . . . . . . . . . . . . . . . . . . . . . .176 9.10.5 pwm control register 2. . . . . . . . . . . . . . . . . . . . . . . . . . .178 9.10.6 dead-time write-once register . . . . . . . . . . . . . . . . . . . . 181 9.10.7 pwm disable mapping write-once register . . . . . . . . . . . 181 9.10.8 fault control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 9.10.9 fault status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 9.10.10 fault acknowledge regist er. . . . . . . . . . . . . . . . . . . . . . . . 186 9.10.11 pwm output control r egister . . . . . . . . . . . . . . . . . . . . . . 187 9.11 pwm glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 table of contents mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor table of contents 11 section 10. monitor rom (mon) 10.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 10.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 10.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192 10.4.1 entering monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 10.4.2 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 10.4.3 echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 10.4.4 break signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 10.4.5 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 10.4.6 baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 10.5 security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 section 11. timer interface a (tima) 11.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 11.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 11.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208 11.4.1 tima counter prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . .208 11.4.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 11.4.3 output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 11.4.3.1 unbuffered output compare . . . . . . . . . . . . . . . . . . . . . 210 11.4.3.2 buffered output com pare . . . . . . . . . . . . . . . . . . . . . . .211 11.4.4 pulse-width modulatio n (pwm) . . . . . . . . . . . . . . . . . . . . . 212 11.4.4.1 unbuffered pwm sig nal generation . . . . . . . . . . . . . . . 213 11.4.4.2 buffered pwm signal generation . . . . . . . . . . . . . . . . . 214 11.4.4.3 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 11.5 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216 11.6 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 advance information mc68hc908mr24 ? rev. 4.1 12 table of contents freescale semiconductor table of contents 11.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 11.7.1 tima clock pin (pte3/tclka) . . . . . . . . . . . . . . . . . . . . . 217 11.7.2 tima channel i/o pins (pte4/tch0a?pte7/tch3a) . . . . . . . . . . . . . . . . . . . 217 11.8 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 11.8.1 tima status an d control register . . . . . . . . . . . . . . . . . . . 218 11.8.2 tima counter registers. . . . . . . . . . . . . . . . . . . . . . . . . . .221 11.8.3 tima counter modulo registers . . . . . . . . . . . . . . . . . . . . 222 11.8.4 tima channel status and control registers . . . . . . . . . . . 222 11.8.5 tima channel registers . . . . . . . . . . . . . . . . . . . . . . . . . . 227 section 12. timer interface b (timb) 12.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 12.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 12.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232 12.4.1 timb counter prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . .233 12.4.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 12.4.3 output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 12.4.3.1 unbuffered output compare . . . . . . . . . . . . . . . . . . . . . 236 12.4.3.2 buffered output com pare . . . . . . . . . . . . . . . . . . . . . . .237 12.4.4 pulse-width modulatio n (pwm) . . . . . . . . . . . . . . . . . . . . . 238 12.4.4.1 unbuffered pwm sig nal generation . . . . . . . . . . . . . . . 239 12.4.4.2 buffered pwm signal generation . . . . . . . . . . . . . . . . . 240 12.4.4.3 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 12.5 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242 12.6 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 12.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 12.7.1 timb clock pin (ptd4/ atd12) . . . . . . . . . . . . . . . . . . . . . 243 12.7.2 timb channel i/o pins (pte1/tch0b?pte2/tch1b) . . . . . . . . . . . . . . . . . . . 243 table of contents mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor table of contents 13 12.8 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 12.8.1 timb status an d control register . . . . . . . . . . . . . . . . . . . 244 12.8.2 timb counter registers. . . . . . . . . . . . . . . . . . . . . . . . . . .247 12.8.3 timb counter modulo registers . . . . . . . . . . . . . . . . . . . . 248 12.8.4 timb channel status and control registers . . . . . . . . . . . 249 12.8.5 timb channel registers . . . . . . . . . . . . . . . . . . . . . . . . . . 253 section 13. serial peripher al interface module (spi) 13.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .255 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 13.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 13.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 13.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258 13.5.1 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 13.5.2 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 13.6 transmission formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262 13.6.1 clock phase and polarity controls. . . . . . . . . . . . . . . . . . . 262 13.6.2 transmission format wh en cpha = 0 . . . . . . . . . . . . . . . 262 13.6.3 transmission format when cpha = 1 . . . . . . . . . . . . . . . 264 13.6.4 transmission initiation latency . . . . . . . . . . . . . . . . . . . . . 265 13.7 error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 13.7.1 overflow error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 13.7.2 mode fault error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 13.8 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271 13.9 resetting the spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 13.10 queuing transmissi on data . . . . . . . . . . . . . . . . . . . . . . . . . . 274 13.11 low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 13.12 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 13.12.1 miso (master in/slave out) . . . . . . . . . . . . . . . . . . . . . . . . 276 13.12.2 mosi (master out/slave in) . . . . . . . . . . . . . . . . . . . . . . . . 277 13.12.3 spsck (serial clock). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 advance information mc68hc908mr24 ? rev. 4.1 14 table of contents freescale semiconductor table of contents 13.12.4 ss (slave select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 13.12.5 v ss (clock ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279 13.13 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 13.13.1 spi control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 13.13.2 spi status and control register . . . . . . . . . . . . . . . . . . . . 282 13.13.3 spi data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 section 14. serial co mmunications interface module (sci) 14.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287 14.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 14.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 14.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289 14.4.1 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 14.4.2 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 14.4.2.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 14.4.2.2 character transmission . . . . . . . . . . . . . . . . . . . . . . . . . 293 14.4.2.3 break characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 14.4.2.4 idle characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 14.4.2.5 inversion of transm itted output. . . . . . . . . . . . . . . . . . . 295 14.4.2.6 transmitter in terrupts. . . . . . . . . . . . . . . . . . . . . . . . . . .295 14.4.3 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 14.4.3.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 14.4.3.2 character reception . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 14.4.3.3 data sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 14.4.3.4 framing errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 14.4.3.5 receiver wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 14.4.3.6 receiver interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 14.4.3.7 error interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 14.5 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 14.6 sci during break module interrupts. . . . . . . . . . . . . . . . . . . .302 table of contents mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor table of contents 15 14.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 14.7.1 pte2/txd (transmit data). . . . . . . . . . . . . . . . . . . . . . . . . 303 14.7.2 pte1/rxd (receive data ) . . . . . . . . . . . . . . . . . . . . . . . . . 303 14.8 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 14.8.1 sci control regi ster 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 14.8.2 sci control regi ster 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 14.8.3 sci control regi ster 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 14.8.4 sci status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 14.8.5 sci status register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 14.8.6 sci data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 14.8.7 sci baud rate register . . . . . . . . . . . . . . . . . . . . . . . . . . 317 section 15. input/output (i/o) ports 15.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321 15.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 15.3 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 15.3.1 port a data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 15.3.2 data direction register a . . . . . . . . . . . . . . . . . . . . . . . . . 324 15.4 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 15.4.1 port b data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 15.4.2 data direction register b. . . . . . . . . . . . . . . . . . . . . . . . . . 326 15.5 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 15.5.1 port c data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 15.5.2 data direction register c . . . . . . . . . . . . . . . . . . . . . . . . . 328 15.6 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 15.7 port e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 15.7.1 port e data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 15.7.2 data direction register e . . . . . . . . . . . . . . . . . . . . . . . . . 332 15.8 port f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 15.8.1 port f data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 15.8.2 data direction register f . . . . . . . . . . . . . . . . . . . . . . . . . 334 advance information mc68hc908mr24 ? rev. 4.1 16 table of contents freescale semiconductor table of contents section 16. computer op erating properly (cop) 16.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .337 16.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 16.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .338 16.4 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 16.4.1 cgmxclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .339 16.4.2 copctl write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .339 16.4.3 power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 16.4.4 internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340 16.4.5 reset vector fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340 16.4.6 copd (cop disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340 16.5 cop control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340 16.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .341 16.7 monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .341 16.8 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 section 17. external interrupt (irq) 17.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .343 17.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 17.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 17.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .344 17.5 irq pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 17.6 irq status and control register . . . . . . . . . . . . . . . . . . . . . . 348 table of contents mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor table of contents 17 section 18. low-volt age inhibit (lvi) 18.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .349 18.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 18.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 18.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .350 18.4.1 polled lvi operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 18.4.2 forced reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . .351 18.4.3 false reset protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 18.4.4 lvi trip selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 18.5 lvi status and control r egister . . . . . . . . . . . . . . . . . . . . . . . 352 18.6 lvi interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .353 18.7 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 section 19. analog-to-dig ital converter (adc) 19.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355 19.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 19.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 19.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .356 19.4.1 adc port i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 19.4.2 voltage conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358 19.4.3 conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 19.4.4 continuous conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 19.4.5 result justification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 19.4.6 monotonicity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 19.5 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .361 19.6 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 19.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 19.7.1 adc analog power pin (v ddad ) . . . . . . . . . . . . . . . . . . . . 361 19.7.2 adc analog ground pin (v ssad ). . . . . . . . . . . . . . . . . . . .362 19.7.3 adc voltage reference pin (v refh ) . . . . . . . . . . . . . . . . . 362 advance information mc68hc908mr24 ? rev. 4.1 18 table of contents freescale semiconductor table of contents 19.7.4 adc voltage reference low pin (v refl ) . . . . . . . . . . . . . 362 19.7.5 adc voltage in ( advin) . . . . . . . . . . . . . . . . . . . . . . . . . . 362 19.7.6 adc external connections. . . . . . . . . . . . . . . . . . . . . . . . . 362 19.7.6.1 v refh and v refl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 19.7.6.2 anx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 19.7.6.3 grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 19.8 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 19.8.1 adc status and control register. . . . . . . . . . . . . . . . . . . .364 19.8.2 adc data register high . . . . . . . . . . . . . . . . . . . . . . . . . . 367 19.8.3 adc data register low . . . . . . . . . . . . . . . . . . . . . . . . . . .368 19.8.4 adc clock register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 section 20. power-on reset (por) 20.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .371 20.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 20.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .371 section 21. electrical specifications 21.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .373 21.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 21.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 374 21.4 functional operating range. . . . . . . . . . . . . . . . . . . . . . . . . . 375 21.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 21.6 dc electrical characteristics (v dd = 5.0 vdc 10%). . . . . . . 376 21.7 flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . 377 21.8 control timing (v dd = 5.0 vdc 10%) . . . . . . . . . . . . . . . . . 378 21.9 serial peripheral inte rface characteristics (v dd = 5.0 vdc 10%) . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 21.10 timer interface module characterist ics . . . . . . . . . . . . . . . . . 382 table of contents mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor table of contents 19 21.11 clock generation m odule component specific ations . . . . . . 382 21.12 cgm operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . .382 21.13 cgm acquisition/lock ti me specifications . . . . . . . . . . . . 383 21.14 analog-to-digital converter (adc) characteristics. . . . . . . . . 384 section 22. mechanic al specifications 22.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .385 22.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 22.3 64-pin plastic quad flat pack (qfp) . . . . . . . . . . . . . . . . . . . 386 22.4 56-pin shrink dual in -line package (sdip) . . . . . . . . . . . . . . 387 section 23. ordering information 23.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .389 23.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 23.3 order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 glossary advance information mc68hc908mr24 ? rev. 4.1 20 table of contents freescale semiconductor table of contents mc68hc908mr24 ? rev. 4.0 advance information motorola list of figures 21 advance information ? mc68hc908mr24 list of figures figure title page 1-1 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 1-2 64-pin qfp pin assi gnments . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1-3 56-pin sdip pin a ssignments . . . . . . . . . . . . . . . . . . . . . . . . . 34 1-4 power supply bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2-1 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2-2 control, status, and data register s summary. . . . . . . . . . . . . 42 4-1 flash control regist er (flcr) . . . . . . . . . . . . . . . . . . . . . . . 59 4-2 smart programming algorithm . . . . . . . . . . . . . . . . . . . . . . . . . 64 4-3 flash block protect register (flbpr). . . . . . . . . . . . . . . . . . 66 5-1 configuration register (config). . . . . . . . . . . . . . . . . . . . . . . 70 6-1 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6-2 accumulator (a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6-3 index register (h:x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6-4 stack pointer (sp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6-5 program counter (pc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 6-6 condition code register (ccr) . . . . . . . . . . . . . . . . . . . . . . . . 79 7-1 sim block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7-2 cgm clock signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 7-3 external reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 7-4 internal reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7-5 sources of internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7-6 por recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 7-7 interrupt entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 7-8 interrupt processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 advance information mc68hc908mr24 ? rev. 4.0 22 list of figures motorola list of figures figure title page 7-9 interrupt recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 7-10 interrupt recognition example . . . . . . . . . . . . . . . . . . . . . . . . 104 7-11 wait mode entry timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 7-12 wait recovery from interrupt . . . . . . . . . . . . . . . . . . . . . . . . . 106 7-13 wait recovery from internal reset. . . . . . . . . . . . . . . . . . . . . 106 7-14 sim reset status register (srsr) . . . . . . . . . . . . . . . . . . . . 107 8-1 cgm block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 8-2 cgm i/o register summar y. . . . . . . . . . . . . . . . . . . . . . . . . . 113 8-3 cgm external connections . . . . . . . . . . . . . . . . . . . . . . . . . . 121 8-4 cgm i/o register summar y. . . . . . . . . . . . . . . . . . . . . . . . . . 123 8-5 pll control register (pc tl) . . . . . . . . . . . . . . . . . . . . . . . . . 124 8-6 pll bandwidth control register (pbwc) . . . . . . . . . . . . . . . 126 8-7 pll programming register (ppg) . . . . . . . . . . . . . . . . . . . . . 128 9-1 pwm module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . 137 9-2 register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 9-3 center-aligned pwm (positive polarity) . . . . . . . . . . . . . . . . . 141 9-4 edge-aligned pwm (posit ive polarity) . . . . . . . . . . . . . . . . . . 142 9-5 reload frequency change. . . . . . . . . . . . . . . . . . . . . . . . . . .144 9-6 pwm interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 9-7 center-aligned pwm value loading . . . . . . . . . . . . . . . . . . . 146 9-8 center-aligned loading of modulus . . . . . . . . . . . . . . . . . . . .146 9-9 edge-aligned pwm value loading . . . . . . . . . . . . . . . . . . . . 147 9-10 edge-aligned modulus loading . . . . . . . . . . . . . . . . . . . . . . .147 9-11 complementary pairing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 9-12 typical ac motor drive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 9-13 dead-time generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 9-14 effects of dead-time inse rtion . . . . . . . . . . . . . . . . . . . . . . . . 153 9-15 dead-time at duty cycle boundaries . . . . . . . . . . . . . . . . . . 153 9-16 dead-time and small pulse widths . . . . . . . . . . . . . . . . . . . .154 9-17 ideal complementary operation (dead time = 0) . . . . . . . . . 155 9-18 current convention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 9-19 top/bottom correction for pwms 1 and 2 . . . . . . . . . . . . . . . 158 9-20 pwm polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159 9-21 pwm output control r egister (pwmout) . . . . . . . . . . . . . . 160 list of figures mc68hc908mr24 ? rev. 4.0 advance information motorola list of figures 23 figure title page 9-22 dead-time insertion during outctl = 1 . . . . . . . . . . . . . . . 162 9-23 dead-time insertion during outctl = 1 . . . . . . . . . . . . . . . 162 9-24 pwm disable mapping write-once register (dismap) . . . . 163 9-25 pwm disabling scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 9-26 pwm disabling decode sc heme . . . . . . . . . . . . . . . . . . . . . . 166 9-27 pwm disabling in automa tic mode . . . . . . . . . . . . . . . . . . . . 167 9-28 pwm disabling in manual mode (e xample 1) . . . . . . . . . . . . 169 9-29 pwm disabling in manual mode (e xample 2) . . . . . . . . . . . . 169 9-30 pwm software disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 9-31 pwmen and pwm pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 9-32 pwm counter register high (pcnth). . . . . . . . . . . . . . . . . . 173 9-33 pwm counter register low (pcntl) . . . . . . . . . . . . . . . . . . 173 9-34 pwm counter modulo register hi gh (pmodh). . . . . . . . . . . 174 9-35 pwm counter modulo register lo w (pmodl) . . . . . . . . . . . 174 9-36 pwmx value registers high (pvalxh) . . . . . . . . . . . . . . . . . 175 9-37 pwmx value registers low (pvalxl). . . . . . . . . . . . . . . . . . 175 9-38 pwm control register 1 (pctl1) . . . . . . . . . . . . . . . . . . . . . 176 9-39 pwm control register 2 (pctl2) . . . . . . . . . . . . . . . . . . . . . 179 9-40 dead-time write-once register ( deadtm) . . . . . . . . . . . . . 181 9-41 pwm disable mapping write-once register (dismap) . . . . 181 9-42 fault control register (f cr) . . . . . . . . . . . . . . . . . . . . . . . . . 182 9-43 fault status regist er (fsr) . . . . . . . . . . . . . . . . . . . . . . . . . . 184 9-44 fault acknowledge register (ftack) . . . . . . . . . . . . . . . . . . 186 9-45 pwm output control r egister (pwmout) . . . . . . . . . . . . . . 187 9-46 pwm clock cycle and pwm cycle de finitions . . . . . . . . . . . 189 9-47 pwm load cycle/frequency definition . . . . . . . . . . . . . . . . . 190 10-1 monitor mode circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 10-2 monitor data format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 10-3 sample monitor waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 195 10-4 read transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196 10-5 break transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196 10-6 monitor mode entry timing . . . . . . . . . . . . . . . . . . . . . . . . . . .201 advance information mc68hc908mr24 ? rev. 4.0 24 list of figures motorola list of figures figure title page 11-1 tima block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 11-2 tim i/o register summar y . . . . . . . . . . . . . . . . . . . . . . . . . . 206 11-3 pwm period and pulse wi dth . . . . . . . . . . . . . . . . . . . . . . . . 212 11-4 tima status and contro l register (tasc) . . . . . . . . . . . . . . . 218 11-5 tima counter registers (tacnt h and tacntl) . . . . . . . . 221 11-6 tima counter modulo registers (tamodh and tamodl) . . . . . . . . . . . . . . . . . . . . . . . . . 222 11-7 tima channel status and control registers (tasc0?tasc3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 11-8 chxmax latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227 11-9 tima channel registers (tach0 h/l?tach3h/l) . . . . . . . . 228 12-1 timb block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 12-2 timb i/o register summar y. . . . . . . . . . . . . . . . . . . . . . . . . . 234 12-3 pwm period and pulse wi dth . . . . . . . . . . . . . . . . . . . . . . . . 238 12-4 timb status and contro l register (tbsc) . . . . . . . . . . . . . . . 244 12-5 timb counter registers (tbcnt h and tbcntl) . . . . . . . . . 247 12-6 timb counter modulo registers (tbmodh and tbmodl) . . . . . . . . . . . . . . . . . . . . . . . . . 248 12-7 timb channel status and control registers (tbsc0?tbsc1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 12-8 chxmax latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253 12-9 timb channel registers (tbch0 h/l?tbch1h/l) . . . . . . . . 254 13-1 spi module block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . .258 13-2 spi i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . . .259 13-3 full-duplex master-sla ve connections . . . . . . . . . . . . . . . . . 260 13-4 transmission format (cpha = 0) . . . . . . . . . . . . . . . . . . . . . 263 13-5 cpha/ss timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 13-6 transmission format (cpha = 1) . . . . . . . . . . . . . . . . . . . . . 265 13-7 transmission start delay (master) . . . . . . . . . . . . . . . . . . . . . 266 13-8 missed read of overflow condition . . . . . . . . . . . . . . . . . . . .268 13-9 clearing sprf when ovrf interrupt is no t enabled . . . . . . 269 13-10 spi interrupt request g eneration . . . . . . . . . . . . . . . . . . . . . 272 13-11 sprf/spte cpu interrupt timing . . . . . . . . . . . . . . . . . . . . . 274 13-12 cpha/ss timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 list of figures mc68hc908mr24 ? rev. 4.0 advance information motorola list of figures 25 figure title page 13-13 spi control regist er (spcr) . . . . . . . . . . . . . . . . . . . . . . . . . 280 13-14 spi status and control register (s pscr) . . . . . . . . . . . . . . . 282 13-15 spi data register (spdr) . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 14-1 sci module block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . .290 14-2 sci i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . . .290 14-3 sci data formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .291 14-4 sci transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 14-5 sci receiver block diagr am . . . . . . . . . . . . . . . . . . . . . . . . . 296 14-6 receiver data sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 14-7 sci control regist er 1 (scc1). . . . . . . . . . . . . . . . . . . . . . . . 304 14-8 sci control regist er 2 (scc2). . . . . . . . . . . . . . . . . . . . . . . . 307 14-9 sci control regist er 3 (scc3). . . . . . . . . . . . . . . . . . . . . . . . 310 14-10 sci status register 1 (s cs1) . . . . . . . . . . . . . . . . . . . . . . . . 312 14-11 flag clearing sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 14-12 sci status register 2 (s cs2) . . . . . . . . . . . . . . . . . . . . . . . . 316 14-13 sci data register (scdr) . . . . . . . . . . . . . . . . . . . . . . . . . . .317 14-14 sci baud rate register (scbr) . . . . . . . . . . . . . . . . . . . . . . 317 15-1 i/o port register summary . . . . . . . . . . . . . . . . . . . . . . . . . . 322 15-2 port a data register (pta ) . . . . . . . . . . . . . . . . . . . . . . . . . . 324 15-3 data direction register a (ddra) . . . . . . . . . . . . . . . . . . . . . 324 15-4 port a i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 15-5 port b data register (ptb ) . . . . . . . . . . . . . . . . . . . . . . . . . . 326 15-6 data direction register b (ddrb) . . . . . . . . . . . . . . . . . . . . . 326 15-7 port b i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 15-8 port c data register (ptc ) . . . . . . . . . . . . . . . . . . . . . . . . . . 328 15-9 data direction register c (ddrc) . . . . . . . . . . . . . . . . . . . . . 328 15-10 port c i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 15-12 port d input circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 15-11 port d data register (ptd ) . . . . . . . . . . . . . . . . . . . . . . . . . . 330 15-13 port e data register (pte ) . . . . . . . . . . . . . . . . . . . . . . . . . . 331 15-14 data direction register e (ddre) . . . . . . . . . . . . . . . . . . . . . 332 15-15 port e i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 15-16 port f data register (ptf ). . . . . . . . . . . . . . . . . . . . . . . . . . .333 15-17 data direction register f (ddrf) . . . . . . . . . . . . . . . . . . . . . 334 advance information mc68hc908mr24 ? rev. 4.0 26 list of figures motorola list of figures figure title page 15-18 port f i/o circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 16-1 cop block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 16-2 cop i/o register summar y . . . . . . . . . . . . . . . . . . . . . . . . . . 338 16-3 cop control register (copctl) . . . . . . . . . . . . . . . . . . . . . . 340 17-1 irq module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 344 17-2 irq i/o register summary. . . . . . . . . . . . . . . . . . . . . . . . . . .344 17-3 irq interrupt flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 17-4 irq status and control register (iscr) . . . . . . . . . . . . . . . . 348 18-1 lvi module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .350 18-2 lvi i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 18-3 lvi status and control register (l viscr). . . . . . . . . . . . . . . 352 19-1 adc block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 19-2 8-bit truncation m ode error . . . . . . . . . . . . . . . . . . . . . . . . . . 360 19-3 adc status and control register (adscr) . . . . . . . . . . . . . . 364 19-4 adc data register high (adrh) left justifi ed mode . . . . . . 367 19-5 adc data register high (adrh) right justif ied mode . . . . . 367 19-6 adc data register low (adrl) left justifi ed mode . . . . . . . 368 19-7 adc data register low (adrl) right justified mode . . . . . . 368 19-8 adc data register low (adrl) 8-bit mode . . . . . . . . . . . . . 369 19-9 adc clock register (adc lk) . . . . . . . . . . . . . . . . . . . . . . . . 369 21-1 spi master timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380 21-2 spi slave timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 22-1 mc68hc908mr24fu. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386 22-2 mc68hc908mr24b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 mc68hc908mr24 ? rev. 4.0 advance information motorola list of tables 27 advance information ? mc68hc908mr24 list of tables table title page 2-1 vector addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 4-1 charge pump clock frequency . . . . . . . . . . . . . . . . . . . . . . . .61 4-2 erase block sizes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 6-1 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6-2 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7-1 signal name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7-2 pin bit set timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 8-1 variable definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 8-2 vco frequency multiplier (n) selectio n. . . . . . . . . . . . . . . . . 128 9-1 pwm prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 9-2 pwm reload frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 9-3 pwm data overflow and underflow conditions . . . . . . . . . . . 148 9-4 current sense pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 9-5 correction methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 9-6 outx bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 9-7 correction methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 9-8 pwm reload frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 9-9 pwm prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 9-10 outx bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 10-1 mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 10-2 mode differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 10-3 read (read memory) command . . . . . . . . . . . . . . . . . . . . . 197 10-4 write (write memory) command. . . . . . . . . . . . . . . . . . . . . 197 advance information mc68hc908mr24 ? rev. 4.0 28 list of tables motorola list of tables table title page 10-5 iread (indexed read) co mmand . . . . . . . . . . . . . . . . . . . . . 198 10-6 iwrite (indexed write) command . . . . . . . . . . . . . . . . . . . . 198 10-7 readsp (read stack po inter) command . . . . . . . . . . . . . . . 199 10-8 run (run user program) command . . . . . . . . . . . . . . . . . . . 199 11-1 prescaler selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 11-2 mode, edge, and level selection . . . . . . . . . . . . . . . . . . . . . . 226 12-1 prescaler selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 12-2 mode, edge, and level selection . . . . . . . . . . . . . . . . . . . . . . 252 13-1 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 13-2 spi interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271 13-3 spi configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 13-4 spi master baud rate selection . . . . . . . . . . . . . . . . . . . . . . 285 14-1 start bit verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 14-2 data bit recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .299 14-3 stop bit recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .299 14-4 character format selection . . . . . . . . . . . . . . . . . . . . . . . . . . 306 14-5 sci baud rate prescaling . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 14-6 sci baud rate selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 14-7 sci baud rate selection examples . . . . . . . . . . . . . . . . . . . .319 15-1 port a pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 15-2 port b pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 15-3 port c pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 15-4 port d pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 15-5 port e pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 15-6 port f pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 18-1 lviout bit indicati on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 19-1 mux channel select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 19-2 adc clock divide ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370 23-1 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor general description 29 advance information ? mc68hc908mr24 section 1. general description 1.1 contents 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.4 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.5 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.5.1 power supply pins (v dd and v ss ) . . . . . . . . . . . . . . . . . . . . 35 1.5.2 oscillator pins (osc1 and osc2) . . . . . . . . . . . . . . . . . . . . 35 1.5.3 external reset pin (rst ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 1.5.4 external interrupt pin (irq ) . . . . . . . . . . . . . . . . . . . . . . . . . 36 1.5.5 cgm power supply pins (v dda and v ssa ) . . . . . . . . . . . . . 36 1.5.6 external filter capac itor pin (cgmxfc) . . . . . . . . . . . . . . . 36 1.5.7 analog power supply pins (v ddad and v ssad ). . . . . . . . . . 36 1.5.8 adc voltage decoup ling capacitor pin (v refh ) . . . . . . . . . 36 1.5.9 adc voltage reference low pin (v refl ) . . . . . . . . . . . . . . 37 1.5.10 port a input/output (i/o) pins (pta7?pta0) . . . . . . . . . . . . 37 1.5.11 port b i/o pins (ptb7/atd7?ptb 0/atd0) . . . . . . . . . . . . . 37 1.5.12 port c i/o pins (ptc6?ptc2 and ptc1/atd9?ptc0/atd8) . . . . . . . . . . . . . . . . . . . . 37 1.5.13 port d input-only pins (ptd6/is3 ?ptd4/is1 and ptd3/fault4?ptd0/fault1) . . . . . . . . . . . . . . . . 37 1.5.14 pwm pins (pwm6?pwm1) . . . . . . . . . . . . . . . . . . . . . . . . . 38 1.5.15 pwm ground pin (pwmgn d) . . . . . . . . . . . . . . . . . . . . . . . 38 1.5.16 port e i/o pins (pte7/tch3a?pte3/tclka and pte2/tch1b?pte0/tclkb). . . . . . . . . . . . . . . . . . 38 1.5.17 port f i/o pins (ptf5/txd?ptf4/rxd and ptf3/miso?ptf0/ spsck) . . . . . . . . . . . . . . . . . . . 38 advance information mc68hc908mr24 ? rev. 4.1 30 general description freescale semiconductor general description 1.2 introduction the mc68hc908mr24 is a member of the low-cost, high-performance m68hc08 family of 8-bi t microcontroller units (mcus). the m68hc08 family is based on the customer-spec ified integrated circuit (csic) design strategy. all mcus in t he family use the enhanced m68hc08 central processor unit (cpu08) and are available with a variety of modules, memory sizes and types, and package types. 1.3 features features of the mc 68hc908mr24 include: high-performance m68hc08 architecture fully upward-compatible objec t code with m6805, m146805, and m68hc05 families 8-mhz internal bus frequency 24 kbytes of on-chip electrically erasable in-circu it programmable read-only memory (flash) on-chip programming firmwa re for use with host personal computer flash data security 1 768 bytes of on-chip r andom-access memory (ram) 12-bit, 6-channel center-alig ned or edge-aligned pulse-width modulator (pwmmc) serial peripheral in terface module (spi) serial communications interface module (sci) 16-bit, 4-channel timer interface module (tima) 16-bit, 2-channel timer interface module (timb) clock generator module (cgm) 1. no security feature is absolutely secure. howe ver, freescale?s strategy is to make reading or copying the flash difficult for unauthorized users. general description mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor general description 31 low-voltage inhibit (lvi) module with software selectable trip points 10-bit, 10-channel analog-to-digital converter (adc) system protection features: ? optional computer operati ng properly (cop) reset ? low-voltage detection with optional reset ? illegal opcode detecti on with optional reset ? illegal address detecti on with optional reset ? fault detection with opt ional pwm disabling 64-pin plastic quad flat pack (qfp) 56-pin shrink dual in-line package (sdip) low-power design (fully static with wait mode) master reset pin (rst ) and power-on reset (por) features of the cpu08 include: enhanced hc05 programming model extensive loop control functions 16 addressing modes (eight more than the hc05) 16-bit index register and stack pointer memory-to-memory data transfers fast 8 8 multiply instruction fast 16/8 divide instruction binary-coded decimal (bcd) instructions optimization for controller applications c language support 1.4 mcu block diagram figure 1-1 shows the structure of the mc68hc908mr24. advance information mc68hc908mr24 ? rev. 4.1 32 general description freescale semiconductor general description figure 1-1. mcu block diagram clock generator module system integration module serial communications interface module serial peripheral interface module (2) timer interface module a low-voltage inhibit module power-on reset module computer operating properly module arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers ? 112 bytes user flash ? 24,064 bytes user ram ? 768 bytes monitor rom ? 240 bytes user flash vector space ? 46 bytes irq module power pta ddra ddrb ptb ddrc ptc ptd ddre pte ptf ddrf internal bus osc1 osc2 cgmxfc rst irq v ss v dd v dda pta7?pta0 pte7/tch3a pte6/tch2a pte5/tch1a pte4/tch0a pte3/tclka pte2/tch1b (1) pte1/tch0b (1) pte0/tclkb (1) ptf5/txd ptf4/rxd ptf3/miso (1) ptf2/mosi (1) ptf1/ss (1) ptf0/spsck (1) timer interface module b pulse--width modulator module ptb7/atd7 ptb6/atd6 ptb5/atd5 ptb4/atd4 ptb3/atd3 ptb2/atd2 ptb1/atd1 ptb0/atd0 ptc6 ptc5 ptc4 ptc3 ptc2 ptc1/atd9 (1) ptc0/atd8 ptd6/is3 ptd5/is2 ptd4/is1 ptd3/fault4 ptd2/fault3 ptd1/fault2 ptd0/fault1 pwm6?pwm1 analog-to-digital converter module v ssa v ddad v ssad (3) pwmgnd v refl (3 v refh notes: 1. these pins are not available in the 56-pin sdip package. 2. this module is not available in the 56-pin sdip package. 3. in the 56-pin sdip package these pins are bonded together. general description mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor general description 33 1.5 pin assignments figure 1-2 shows the 64-pin qf p pin assignments and figure 1-3 shows the 56-pin sdip pin assignments. figure 1-2. 64- pin qfp pin assignments ptc1/atd9 pta2 v ss ptc0/atd8 ptb7/atd7 ptb6/atd6 ptb5/atd5 ptb4/atd4 ptb3/atd3 ptb2/atd2 v ddad v ssad v refl v refh ptc2 ptc3 ptc4 ptc5 irq ptf5/txd ptf4/rxd ptf3/miso ptf2/mosi ptf1/ss ptf0/spsck v dd pte7/tch3a pte6/tch2a pte5/tch1a pte4/tch0a pte3/tclka pte2/tch1b pte1/tch0b pta1 pta0 v ssa osc2 osc1 cgmxfc v dda rst ptb1/atd1 ptb0/atd0 pta7 pta6 pta5 pta4 pta3 ptd1/fault2 ptc6 ptd0/fault1 ptd2/fault3 ptd3/fault4 ptd4/is1 ptd5/is2 ptd6/is3 pwm1 pwm2 pwm3 pwm4 pte0/tclkb 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 pwmgnd pwm5 pwm6 advance information mc68hc908mr24 ? rev. 4.1 34 general description freescale semiconductor general description figure 1-3. 56-pin sd ip pin assignments pta2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 pta3 pta4 pta5 pta6 pta7 ptb0/atd0 ptb1/atd1 ptb2/atd2 ptb3/atd3 ptb4/atd4 ptb5/atd5 ptb6/atd5 ptb7/atd7 ptc0/atd8 v ddad v ssad /v refl v refh ptc2 ptc3 ptc4 ptc5 ptc6 ptd0/fault1 ptd1/fault2 ptd2/fault3 ptd3/fault4 ptd4/is1 ptd5/is2 ptd6/is3 pwm1 pwm2 pwm3 pwm4 pwmgnd pwm5 pwm6 nc pte3/tclka pte4/tch0a pte5/tch1a pte6/tch2a pte7/tch3a v dd v ss ptf4/rxd ptf5/txd irq rst v dda cgmxfc osc1 osc2 v ssa pta0 pta1 note: ptc1, pte0, pt e1, pte2, ptf0, pt f1, ptf2, and ptf3 are removed from this package. general description mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor general description 35 1.5.1 power supply pins (v dd and v ss ) v dd and v ss are the power supply and ground pins. the mcu operates from a single power supply. fast signal transitions on mcu pins place high, short-duration current demands on the power supply. to preven t noise problems, take special care to provide power suppl y bypassing at the mcu as figure 1-4 shows. place the c1 bypass capacitor as close to the mcu as possible. use a high-frequency-response cerami c capacitor for c1. c2 is an optional bulk current bypa ss capacitor for use in appl ications that require the port pins to sour ce high current levels. figure 1-4. power supply bypassing 1.5.2 oscillator pins (osc1 and osc2) the osc1 and osc2 pins ar e the connections for the on-chip oscillator circuit. for more detailed information, see section 8. cl ock generator module (cgm) . mcu v dd c2 c1 0.1 f v ss v dd + note: component values shown represent typical applications. 1?10 f advance information mc68hc908mr24 ? rev. 4.1 36 general description freescale semiconductor general description 1.5.3 external reset pin (rst ) a logic 0 on the rst pin forces the mcu to a known startup state. rst is bidirectional, allowing a reset of t he entire system. it is driven low when any internal reset sour ce is asserted. see section 7. system integration module (sim) . 1.5.4 external interrupt pin (irq ) irq is an asynchronous exte rnal interrupt pin (see section 17. external interrupt (irq) ). 1.5.5 cgm power supply pins (v dda and v ssa ) v dda and v ssa are the power supply pins for the analog portion of the clock generator module (cgm). decoupl ing of these pins should be as per the digital supply. see section 8. clock gener ator module (cgm) . 1.5.6 external filter capacitor pin (cgmxfc) cgmxfc is an external filter capacito r connection for the cgm. see section 8. clock gene rator module (cgm) . 1.5.7 analog power supply pins (v ddad and v ssad ) v ddad and v ssad are the power supply pins for the analog-to-digital converter. decoupling of these pins should be as per the digital supply. see section 19. anal og-to-digital converter (adc) . 1.5.8 adc voltage decoupling capacitor pin (v refh ) v refh is the power supply for sett ing the reference voltage v refh. connect the v refh pin to the same voltage potential as v ddad . see section 19. analog-to-dig ital converter (adc) . general description mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor general description 37 1.5.9 adc voltage reference low pin (v refl ) v refl is the lower reference supp ly for the adc. connect the v refl pin to the same voltage potential as v ssad . see section 19. analog-to-digital converter (adc) . 1.5.10 port a input/ou tput (i/o) pins (pta7 ? pta0) pta7?pta0 are general-purpose bidire ctional input/output (i/o) port pins. see section 15. input/o utput (i/o) ports . 1.5.11 port b i/o pi ns (ptb7/atd7?ptb0/atd0) port b is an 8-bit special function port that shares all eight pins with the analog-to-digital conv erter (adc). see section 19. anal og-to-digital converter (adc) and section 15. input/o utput (i/o) ports . 1.5.12 port c i/o pins (ptc 6?ptc2 and ptc1/a td9?ptc0/atd8) ptc6?ptc2 are general-purpose bidi rectional i/o port pins. (see section 15. input/output (i/o) ports .) ptc1/atd9?ptc0/atd8 are special function port pi ns that are shared with the analog-to-digital converter (adc). see section 19. analog-to-d igital converter (adc) and section 15. input/output (i/o) ports . 1.5.13 port d input -only pins (ptd6/is3 ?ptd4/is1 and ptd3/fault4?ptd0/fault1) ptd6/is3 ?ptd4/is1 are special function input-o nly port pins that also serve as current sensing pins fo r the pulse-width modulator module (pwmmc). ptd3/fault4?ptd0/fault1 are special function port pins that also serve as fault pins for the pwmmc. see section 9. pulse-width modulator fo r motor control (pwmmc) and section 15. input/output (i/o) ports . advance information mc68hc908mr24 ? rev. 4.1 38 general description freescale semiconductor general description 1.5.14 pwm pins (pwm6?pwm1) pwm6?pwm1 are dedicated pins used for the outputs of the pulse-width modulator m odule (pwmmc). these are high-current sink pins. see section 9. pulse-width m odulator for motor control (pwmmc) and section 21. electri cal specifications . 1.5.15 pwm gr ound pin (pwmgnd) pwmgnd is the ground pin for the pulse-width modulator module (pwmmc). this dedicated ground pin is used as the ground for the six high-current pwm pins. see section 9. pulse-wi dth modulator for motor control (pwmmc) . 1.5.16 port e i/o pi ns (pte7/tch3a?pte3/tclka and pte2/tch1b?pte0/tclkb) port e is an 8-bit special function port that shares its pins with the two timer interface modules (tima and timb). see section 11. timer interface a (tima) , section 12. timer interface b (timb) , and section 15. input/output (i/o) ports . 1.5.17 port f i/ o pins (ptf5/txd?ptf4/rxd and ptf3/miso?ptf0/spsck) port f is a 6-bit special function port t hat shares two of its pins with the serial communications interface modu le (sci) and four of its pins with the serial peripheral inte rface module (spi). see section 13. serial peripheral interf ace module (spi) , section 14. serial communications interface module (sci) , and section 15. input/output (i/o) ports . mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor memory map 39 advance information ? mc68hc908mr24 section 2. memory map 2.1 contents 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.3 unimplemented memory loc ations . . . . . . . . . . . . . . . . . . . . . 39 2.4 reserved memory locations . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.5 i/o section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.6 monitor rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 2.2 introduction the cpu08 can address 64 kbytes of memory space. the memory map, shown in figure 2-1 , includes: 24 kbytes of flash 768 bytes of random-access memory (ram) 46 bytes of user-defined vectors 240 bytes of monitor r ead-only memory (rom) 2.3 unimplemented memory locations some addresses are unimplement ed. accessing an unimplemented address can cause an illega l address reset. in t he memory map and in the input/output (i/o) register summary, uni mplemented addresses are shaded. some i/o bits are read only; the write function is unimplemented. writing to a read-only i/o bit has no effect on mcu operation. in register figures, the write function of read- only bits is shaded. similar ly, some i/o bits are advance information mc68hc908mr24 ? rev. 4.1 40 memory map freescale semiconductor memory map write only; the read func tion is unimplemented. re ading of write-only i/o bits has no effect on mc u operation. in register figures, the read function of write-only bits is shaded. 2.4 reserved memory locations some addresses are reserved. writ ing to a reserv ed address can have unpredictable effects on mcu operation. in the memory map, figure 2-1 , and in the i/o register summary, figure 2-2 , reserved addresses are marked with the word reserved. some i/o bits are reserved. writ ing to a reserved bit can have unpredictable effects on mc u operation. in regist er figures, reserved bits are marked wi th the letter r. 2.5 i/o section addresses $0000?$005f, shown in figure 2-2 , contain most of the control, status, and data registers. additional i/o registers have these addresses: $fe01, sim reset stat us register (srsr) $fe08, flash contro l register (flcr) $fe0f, lvi status and co ntrol register (lviscr) $ff80, flash block prot ect register (flbpr) $ffff, cop control register (copctl) memory map mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor memory map 41 $0000 i/o registers ? 96 bytes $005f $0060 ram ? 768 bytes $035f $0360 unimplemented ? 40,096 bytes $9fff $a000 flash ? 24,064 bytes $fdff $fe00 reserved $fe01 sim reset status register (srsr) $fe02 reserved $fe03 reserved $fe04 reserved $fe05 reserved $fe06 reserved $fe07 reserved $fe08 flash control register (flcr) $fe09 unimplemented $fe0a unimplemented $fe0b unimplemented $fe0c unimplemented $fe0d unimplemented $fe0e unimplemented $fe0f lvi status and control register (lviscr) $fe10 monitor rom ? 240 bytes $feff $ff00 unimplemented ? 112 bytes $ff7f $ff80 flash block protect register $ff81 unimplemented ? 80 bytes $ffd1 $ffd2 vectors ? 46 bytes $ffff figure 2-1. memory map advance information mc68hc908mr24 ? rev. 4.1 42 memory map freescale semiconductor memory map addr. register name bit 7 6 5 4 3 2 1 bit 0 $0000 port a data register (pta) see page 324. read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset $0001 port b data register (ptb) see page 326. read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset $0002 port c data register (ptc) see page 328. read: 0 ptc6 ptc5 ptc4 ptc3 ptc2 ptc1 ptc0 write: r reset: unaffected by reset $0003 port d data register (ptd) see page 330. read: 0 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: r r r r r r r r reset: unaffected by reset $0004 data direction register a (ddra) see page 324. read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset: 0 0 0 0 0 0 0 0 $0005 data direction register b (ddrb) see page 326. read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset: 0 0 0 0 0 0 0 0 $0006 data direction register c (ddrc) see page 328. read: 0 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: r reset: 0 0 0 0 0 0 0 0 $0007 unimplemented $0008 port e data register (pte) see page 331. read: pte7 pte6 pte5 pte4 pte3 pte2 pte1 pte0 write: reset: unaffected by reset $0009 port f data register (ptf) see page 333. read: 0 0 ptf5 ptf4 ptf3 ptf2 ptf1 ptf0 write: r r reset: unaffected by reset u = unaffected x = indeterminate r = reserved bold = buffered figure 2-2. control, status, and data registers summary (sheet 1 of 10) memory map mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor memory map 43 $000a unimplemented $000b unimplemented $000c data direction register e (ddre) see page 332. read: ddre7 ddre6 ddre5 ddre4 ddre3 ddre2 ddre1 ddre0 write: reset: 0 0 0 0 0 0 0 0 $000d data direction register f (ddrf) see page 334. read: 0 0 ddrf5 ddrf4 ddrf3 ddrf2 ddrf1 ddrf0 write: r r reset: 0 0 0 0 0 0 $000e tima status/control register (tasc) see page 218. read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst r reset: 0 0 1 0 0 0 0 0 $000f tima counter register high (tacnth) see page 221. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: r r r r r r r r reset: 0 0 0 0 0 0 0 0 $0010 tima counter register low (tacntl) see page 221. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: r r r r r r r r reset: 0 0 0 0 0 0 0 0 $0011 tima counter modulo register high (tamodh) see page 222. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 1 1 1 1 1 1 1 1 $0012 tima counter modulo register low (tamodl) see page 222. read: bit 7 6 5 4 3 2 1 bit 0 write: reset: 1 1 1 1 1 1 1 1 $0013 tima channel 0 status/control register (tasc0) see page 228. read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset: 0 0 0 0 0 0 0 0 $0014 tima channel 0 register high (tach0h) see page 228. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset addr. register name bit 7 6 5 4 3 2 1 bit 0 u = unaffected x = indeterminate r = reserved bold = buffered figure 2-2. control, status, and data registers summary (sheet 2 of 10) advance information mc68hc908mr24 ? rev. 4.1 44 memory map freescale semiconductor memory map $0015 tima channel 0 register low (tach0l) see page 228. read: bit 7 6 5 4 3 2 1 bit 0 write: reset: indeterminate after reset $0016 tima channel 1 status/control register (tasc1) see page 228. read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 r reset: 0 0 0 0 0 0 0 0 $0017 tima channel 1 register high (tach1h) see page 228. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0018 tima channel 1 register low (tach1l) see page 228. read: bit 7 6 5 4 3 2 1 bit 0 write: reset: indeterminate after reset $0019 tima channel 2 status/control register (tasc2) see page 223. read: ch2f ch2ie ms2b ms2a els2b els2a tov2 ch2max write: 0 reset: 0 0 0 0 0 0 0 0 $001a tima channel 2 register high (tach2h) see page 228. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $001b tima channel 2 register low (tach2l) see page 228. read: bit 7 6 5 4 3 2 1 bit 0 write: reset: indeterminate after reset $001c tima channel 3 status/control register (tasc3) see page 223. read: ch3f ch3ie 0 ms3a els3b els3a tov3 ch3max write: 0 r reset: 0 0 0 0 0 0 0 0 $001d tima channel 3 register high (tach3h) see page 228. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $001e tima channel 3 register low (tach3l) see page 228. read: bit 7 6 5 4 3 2 1 bit 0 write: reset: indeterminate after reset addr. register name bit 7 6 5 4 3 2 1 bit 0 u = unaffected x = indeterminate r = reserved bold = buffered figure 2-2. control, status, and data registers summary (sheet 3 of 10) memory map mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor memory map 45 $001f configuration register (config) see page 70. read: edge botneg topneg indep lvirst lvipwr bit 1 copd write: reset: 0 0 0 0 1 1 0 0 $0020 pwm control register 1 (pctl1) see page 176. read: disx disy pwmint pwmf isens1 isens0 ldok pwmen write: reset: 0 0 0 0 0 0 0 0 $0021 pwm control register 2 (pctl2) see page 179. read: ldfq1 ldfq0 0 ipol1 ipol2 ipol3 prsc1 prsc0 write: reset: 0 0 0 0 0 0 0 0 $0022 fault control register (fcr) see page 182. read: fint4 fmode4 fint3 fmode3 fint2 fmode2 fint1 fmode1 write: reset: 0 0 0 0 0 0 0 0 $0023 fault status register (fsr) see page 184. read: fpin4 fflag4 fpin3 fflag3 fpin2 fflag2 fpin1 fflag1 write: reset: u 0 u 0 u 0 u 0 $0024 fault acknowledge register (ftack) see page 186. read: 0 0 dt6 dt5 dt4 dt3 dt2 dt1 write: ftack4 ftack3 ftack2 ftack1 reset: 0 0 0 0 0 0 0 0 $0025 pwm output control register (pwmout) see page 187. read: 0 outctl out6 out5 out4 out3 out2 out1 write: reset: 0 0 0 0 0 0 0 0 $0026 pwm counter register high (pcnth) see page 173. read: 0 0 0 0 bit 11 bit 10 bit 9 bit 8 write: reset: 00 0 0 0 0 00 $0027 pwm counter register low (pcntl) see page 173. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 00 0 0 0 0 00 $0028 pwm counter modulo register high (pmodh) see page 174. read: 0 0 0 0 bit 11 bit 10 bit 9 bit 8 write: reset: 00 0 0 x x xx addr. register name bit 7 6 5 4 3 2 1 bit 0 u = unaffected x = indeterminate r = reserved bold = buffered figure 2-2. control, status, and data registers summary (sheet 4 of 10) advance information mc68hc908mr24 ? rev. 4.1 46 memory map freescale semiconductor memory map $0029 pwm counter modulo register low (pmodl) see page 174. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: xx x x x x xx $002a pwm 1 value register high (pval1h) see page 175. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 $002b pwm 1 value register low (pval1l) see page 175. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $002c pwm 2 value register high (pval2h) see page 175. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 $002d pwm 2 value register low (pval2l) see page 175. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $002e pwm 3 value register high (pval3h) see page 175. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 $002f pwm 3 value register low (pval3l) see page 175. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $0030 pwm 4 value register high (pval4h) see page 175. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 $0031 pwm 4 value register low (pval4l) see page 175. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $0032 pwm 5 value register high (pmval5h) see page 175. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 addr. register name bit 7 6 5 4 3 2 1 bit 0 u = unaffected x = indeterminate r = reserved bold = buffered figure 2-2. control, status, and data registers summary (sheet 5 of 10) memory map mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor memory map 47 $0033 pwm 5 value register low (pval5l) see page 175. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $0034 pwm 6 value register high (pval6h) see page 175. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 $0035 pwm 6 value register low (pmval6l) see page 175. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $0036 dead-time write-once register (deadtm) see page 181. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 1 1 1 1 1 1 1 1 $0037 pwm disable mapping write-once register (dismap) see page 181. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 1 1 1 1 1 1 1 1 $0038 sci control register 1 (scc1) see page 304. read: loops ensci txinv m wake ilty pen pty write: reset: 0 0 0 0 0 0 0 0 $0039 sci control register 2 (scc2) see page 307. read: sctie tcie scrie ilie te re rwu sbk write: reset: 0 0 0 0 0 0 0 0 $003a sci control register 3 (scc3) see page 310. read: r8 t8 00 orie neie feie peie write: r r r reset: u u 0 0 0 0 0 0 $003b sci status register 1 (scs1) see page 312. read: scte tc scrf idle or nf fe pe write: r r r r r r r r reset: 1 1 0 0 0 0 0 0 $003c sci status register 2 (scs2) see page 316. read: 0 0 0 0 0 0 bkf rpf write: r r r r r r r r reset: 0 0 0 0 0 0 0 0 addr. register name bit 7 6 5 4 3 2 1 bit 0 u = unaffected x = indeterminate r = reserved bold = buffered figure 2-2. control, status, and data registers summary (sheet 6 of 10) advance information mc68hc908mr24 ? rev. 4.1 48 memory map freescale semiconductor memory map $003d sci data register (scdr) see page 317. read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset $003e sci baud rate register (scbr) see page 317. read: 0 0 scp1 scp0 0 scr2 scr1 scr0 write: r r r reset: 0 0 0 0 0 0 0 0 $003f irq status/control register (iscr) see page 348. read: 0 0 0 0 irqf 0 imask1 mode1 write: r r r r ack1 reset: 0 0 0 0 0 0 0 0 $0040 adc status and control register (adscr) see page 364. read: coco aien adco adch4 adch3 adch2 adch1 adch0 write: reset: 0 0 0 1 1 1 1 1 $0041 adc data register high (adrh) see page 367. read: 0 0 0 0 0 0 ad9 ad8 write: r r r r r r r r reset: unaffected by reset $0042 adc data register low (adrl) see page 368. read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write: r r r r r r r r reset: unaffected by reset $0043 adc clock register (adclk) see page 369. read: adiv2 adiv1 adiv0 adiclk mode1 mode0 0 0 write: r reset: 0 1 1 1 0 0 0 0 $0044 spi control register (spcr) see page 280. read: sprie r spmstr cpol cpha spwom spe sptie write: reset: 0 0 1 0 1 0 0 0 $0045 spi status and control register (spscr) see page 282. read: sprf errie ovrf modf spte modfen spr1 spr0 write: r r r r reset: 0 0 0 0 1 0 0 0 $0046 spi data register (spdr) see page 285. read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset addr. register name bit 7 6 5 4 3 2 1 bit 0 u = unaffected x = indeterminate r = reserved bold = buffered figure 2-2. control, status, and data registers summary (sheet 7 of 10) memory map mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor memory map 49 $0047 unimplemented $0050 unimplemented $0051 timb status/control register (tbsc) see page 244. read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst r reset: 0 0 1 0 0 0 0 0 $0052 timb counter register high (tbcnth) see page 247. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: r r r r r r r r reset: 0 0 0 0 0 0 0 0 $0053 timb counter register low (tbcntl) see page 247. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: r r r r r r r r reset: 0 0 0 0 0 0 0 0 $0054 timb counter modulo register high (tbmodh) see page 248. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 1 1 1 1 1 1 1 1 $0055 timb counter modulo register low (tbmodl) see page 248. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 1 1 1 1 1 1 1 1 $0056 timb channel 0 status/control register (tbsc0) see page 249. read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset: 0 0 0 0 0 0 0 0 $0057 timb channel 0 register high (tbch0h) see page 254. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset $0058 timb channel 0 register low (tbch0l) see page 254. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset addr. register name bit 7 6 5 4 3 2 1 bit 0 u = unaffected x = indeterminate r = reserved bold = buffered figure 2-2. control, status, and data registers summary (sheet 8 of 10) advance information mc68hc908mr24 ? rev. 4.1 50 memory map freescale semiconductor memory map $0059 timb channel 1 status/control register (tbsc1) see page 249. read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 r reset: 0 0 0 0 0 0 0 0 $005a timb channel 1 register high (tbch1h) see page 254. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset $005b timb channel 1 register low (tbch1l) see page 254. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset $005c pll control register (pctl) see page 124. read: pllie pllf pllon bcs 1111 write: r r r r r reset: 0 0 1 0 1 1 1 1 $005d pll bandwidth control register (pbwc) see page 126. read: auto lock acq xld 0000 write: r r r r r reset: 0 0 0 0 0 0 0 0 $005e pll programming register (ppg) see page 128. read: mul7 mul6 mul5 mul4 vrs7 vrs6 vrs5 vrs4 write: reset: 0 1 1 0 0 1 1 0 $005f unimplemented $fe00 unimplemented $fe01 sim reset status register (srsr) see page 107. read: por pin cop ilop ilad 0 lvi 0 write: r r r r r r r r reset: 1 0 0 0 0 0 0 0 $fe03 unimplemented $fe08 flash control register (flcr) see page 59. read: fdiv1 fdiv0 blk1 blk0 hven margin erase pgm write: reset: 0 0 0 0 0 0 0 0 addr. register name bit 7 6 5 4 3 2 1 bit 0 u = unaffected x = indeterminate r = reserved bold = buffered figure 2-2. control, status, and data registers summary (sheet 9 of 10) memory map mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor memory map 51 $fe0f lvi status and control register (lviscr) see page 352. read: lviout 0 trpsel 00000 write: r r r r r r r reset: 0 0 0 0 0 0 0 0 $ff80 flash block protect register (flbpr) see page 66. read: 0 0 0 0 bpr3 bpr2 bpr1 bpr0 write: reset: 0 0 0 0 0 0 0 0 $ffff cop control register (copctl) see page 340. read: low byte of reset vector write: clear cop counter reset: unaffected by reset addr. register name bit 7 6 5 4 3 2 1 bit 0 u = unaffected x = indeterminate r = reserved bold = buffered figure 2-2. control, status, and data registers summary (sheet 10 of 10) advance information mc68hc908mr24 ? rev. 4.1 52 memory map freescale semiconductor memory map table 2-1 is a list of vector locations. table 2-1. vector addresses address vector low $ffd2 sci transmit vector (high) $ffd3 sci transmit vector (low) $ffd4 sci receive vector (high) $ffd5 sci receive vector (low) $ffd6 sci error vector (high) $ffd7 sci error vector (low) $ffd8 spi transmit vector (high) (1) $ffd9 spi transmit vector (low) (1) $ffda spi receive vector (high) (1) $ffdb spi receive vector (low) (1) $ffdc a/d vector (high) $ffdd a/d vector (low) $ffde tim b overflow vector (high) $ffdf tim b overflow vector (low) $ffe0 tim b channel 1 vector (high) $ffe1 tim b channel 1 vector (low) $ffe2 tim b channel 0 vector (high) $ffe3 tim b channel 0 vector (low) $ffe4 tim a overflow vector (high) $ffe5 tim a overflow vector (low) $ffe6 tim a channel 3 vector (high) $ffe7 tim a channel 3 vector (low) $ffe8 tim a channel 2 vector (high) $ffe9 tim a channel 2 vector (low) $ffea tim a channel 1 vector (high) $ffeb tim a channel 1 vector (low) $ffec tim a channel 0 vector (high) $ffed tim a channel 0 vector (low) 1. the spi module is not availa ble in the 56-pin sdip package. priority memory map mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor memory map 53 2.6 monitor rom the 240 bytes at addresses $fe 10?$feff are reserved rom addresses that contain the instructi ons for the monitor functions. see section 10. monitor rom (mon) . $ffee pwmmc vector (high) $ffef pwmmc vector (low) $fff0 fault 4 (high) $fff1 fault 4 (low) $fff2 fault 3 (high) $fff3 fault 3 (low) $fff4 fault 2 (high) $fff5 fault 2 (low) $fff6 fault 1 (high) $fff7 fault 1 (low) $fff8 pll vector (high) $fff9 pll vector (low) $fffa irq vector (high) $fffb irq vector (low) $fffc swi vector (high) $fffd swi vector (low) high $fffe reset vector (high) $ffff reset vector (low) table 2-1. vector addresses (continued) address vector priority advance information mc68hc908mr24 ? rev. 4.1 54 memory map freescale semiconductor memory map mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor random-access memory (ram) 55 advance information ? mc68hc908mr24 section 3. random-access memory (ram) 3.1 contents 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 3.2 introduction this section describes the 768 bytes of random-access memory (ram). 3.3 functional description addresses $0060?$035f are ram locati ons. the location of the stack ram is programmable. the 16-bit stack pointer a llows the stack to be anywhere in the 64-kb yte memory space. note: for correct operation, the stack pointer must point only to ram locations. within page zero are 160 bytes of ra m. because the location of the stack ram is programmable, all page zero ram locations can be used for input/output (i/o) control and us er data or code. when the stack pointer is moved from its reset location at $00ff, direct addressing mode instructions can access effici ently all page zero ram locations. page zero ram, therefor e, provides ideal lo cations for frequently accessed global variables. before processing an interrupt, the central processor unit (cpu) uses five bytes of the stack to save the contents of t he cpu registers. note: for m68hc05 and m1468hc0 5 compatibility, the h register is not stacked. advance information mc68hc908mr24 ? rev. 4.1 56 random-access memory (ram) freescale semiconductor random-access memory (ram) during a subroutine call, the cpu uses two bytes of the stack to store the return address. the stack po inter decrements during pushes and increments during pulls. note: be careful when using nested subr outines. the cpu ma y overwrite data in the ram during a s ubroutine or during the interrupt stacking operation. mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor flash memory 57 advance information ? mc68hc908mr24 section 4. flash memory 4.1 contents 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 4.4 flash control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.5 flash charge pump frequ ency control . . . . . . . . . . . . . . . . 60 4.6 flash erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.7 flash program/margin r ead operation . . . . . . . . . . . . . . . . . 62 4.8 flash block protecti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.9 flash block protect regist er . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.10 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4.2 introduction this section describes the operat ion of the embedd ed flash memory. this memory can be r ead, programmed, and er ased from a single external supply. the program and er ase operations are enabled through the use of an internal charge pump. 4.3 functional description the flash memory is an array of 24,064 bytes with an additional 46 bytes of user vectors and one byte of block pr otection. an erased bit reads as a logic 0 and a programmed bi t reads as a logic 1. program and erase operations are facilitated thr ough control bits in a memory mapped register. details for th ese operations appear la ter in this section. advance information mc68hc908mr24 ? rev. 4.1 58 flash memory freescale semiconductor flash memory memory in the flash array is organi zed into pages within rows. there are eight pages of me mory per row with ei ght bytes per page. the minimum erase block size is a singl e row, 64 bytes. programming is performed on a per-page basis, eight bytes at a time. the address ranges for the user memory and vectors are: $a000?$fdff $ff80, block protect register (flbpr) $fe08, flash contro l register (flcr) $ffd2?$ffff (these locations are reserved for user-defined interrupt and reset vectors.) when programming the flash , just enough program ti me must be used to program a page. too much program time c an result in a program disturb condition, in which ca se an erased bit on the row being programmed becomes unintentionally programmed. progr am disturb is avoided by using an it erative program and marg in read technique known as the smart page programming algorithm. the smart programming algorithm is required whenever the user is programming the array (see 4.7 flash program/ma rgin read operation ). as well, to avoid the program disturb issue, each row should not be programmed more than ei ght times before it is erased. the eight program cycle maximum per row aligns with the architecture?s eight pages of storage per ro w. the margin read step of the smart programming algorithm is used to ensure programmed bits are programmed to sufficient margin fo r data retention over the device?s lifetime. the row architecture for this array is: $a000?$a03f (row 0) $a040?$a07f (row 1) $a080?$a0cf (row 2) --------------- ------------- $ffbf?$ffff (row 511) note: programming tools are available fr om freescale. contact a local freescale representative for more information. flash memory mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor flash memory 59 note: a security feature prevents vi ewing of the flash contents. 1 4.4 flash control register the flash control register controls flash progr am, erase, and margin read operations. fdiv1 ? frequency di vide control bit this read/write bit togethe r with fdiv0 selects th e factor by which the charge pump clock is divided fr om the system clock. see 4.5 flash charge pump frequency control . fdiv0 ? frequency di vide control bit this read/write bit togethe r with fdiv1 selects th e factor by which the charge pump clock is divided fr om the system clock. see 4.5 flash charge pump frequency control . blk1? block erase control bit this read/write bit together with blk0 allows erasing of blocks of varying size. see 4.6 flash erase operation for a description of available block sizes. blk0 ? block erase control bit this read/write bit together with blk1 allows erasing of blocks of varying size. see 4.6 flash erase operation for a description of available block sizes. 1. no security feature is absolutely secure. howe ver, freescale?s strategy is to make reading or copying the flash difficult for unauthorized users. address: $fe08 bit 7654321bit 0 read: fdiv1 fdiv0 blk1 blk0 hven margin erase pgm write: reset:00000000 figure 4-1. flash cont rol register (flcr) advance information mc68hc908mr24 ? rev. 4.1 60 flash memory freescale semiconductor flash memory hven ? high-volt age enable bit this read/write bit enables the charge pump to dr ive high voltages for program and erase operati ons in the array. hv en can be set only if either pgm = 1 or erase = 1 and the proper sequence for program/margin read or erase is followed. 1 = high voltage enabled to array and charge pump on 0 = high voltage disabled to array and charge pump off margin ? margin read control bit this read/write bit confi gures the memory for ma rgin read operation. margin cannot be set if the hven = 1. margin will automatically return to unset if asse rted when hven is set. 1 = verify operation selected 0 = verify operation unselected erase ? erase control bit this read/write bit conf igures the memory for erase operation. erase is interlocked wit h the pgm bit such that both bits cannot be set at the same time. 1 = erase operation selected 0 = erase operation unselected pgm ? program control bit this read/write bit conf igures the memory fo r program operation. pgm is interlocked with the erase bit such t hat both bits cannot be set at the same time. 1 = program operation selected 0 = program operation unselected 4.5 flash charge pump frequency control the internal charge pump required for program, margin read, and erase operations is designed to operate most efficiently with a 2-mhz clock. the charge pump clock is der ived from the bus clock. table 4-1 shows how the fdiv bits are used to select a charge pump frequency based on the bus clock frequency. program and erase o perations cannot be performed if the bus clock frequency is below 2 mhz. flash memory mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor flash memory 61 4.6 flash erase operation use this step-by-step procedure to erase a bl ock of flash memory: 1. set the erase bit, the blk0, blk1, fdiv0, and fdiv1 bits in the flash control register. see table 4-2 for block sizes. see table 4-1 for fdiv settings. 2. to ensure this target portion of the array is unprotected, read the block protect regist er address $ff80. see 4.8 flash block protection and 4.9 flash block protect register for more information. 3. write to any flash address wi th any data within the block address rang e desired. 4. set the hven bit. 5. wait for a time, t erase . 6. clear the hven bit. 7. wait for a time, t kill, for the high voltages to dissipate. 8. clear the erase bit. 9. after a time, t hvd , the memory can be accessed in read mode again. note: while these operations mu st be performed in th e order shown, other unrelated operations may occur betwe en the steps. once the hven bit is set, the array cannot be read. mask interrupts prior to setting the hven bit. table 4-1. charge pump clock frequency fdiv1 fdiv0 pump clock frequency bus clock frequency 0 0 bus frequency 1 1.8 mhz?2.5 mhz 0 1 bus frequency 2 3.6 mhz?5 mhz 1 0 bus frequency 2 3.6 mhz?5 mhz 1 1 bus frequency 4 7.2 mhz ?8 mhz advance information mc68hc908mr24 ? rev. 4.1 62 flash memory freescale semiconductor flash memory table 4-2 shows the various block sizes which can be erased in one erase operation. in step 2 of the erase operation, the cared addr esses are latched and used to determine the locati on of the block to be erased. for instance, with blk0 = blk1 = 0, writi ng to any flash addr ess in the range $a000?$ffff will enable the full-array erase. 4.7 flash program/margin read operation note: after a total of eight program operations have been applied to a row, the row must be erased bef ore further programming to avoid program disturb. an erased byte will read $00. programming of the flash memo ry is done on a page basis. a page consists of eight consecutive byte s starting from address $xxx0 or $xxx8. the purpose of the ma rgin read mode is to ensure that data has been programmed with suffic ient margin for long- term data retention. while performing a margin read, t he operation is the same as for ordinary read mode except that a bui lt-in counter stre tches the data access for an additional eight cycles to allow sensing of the lower cell current. margin read mode imposes a more stringent read condition on the bit cell to ensure th at the bit cell is programmed with enough margin for long-term data retention. during these eight cycles the cop counter continues to run. the user must ac count for these extra cycles within cop feed loops. a margin read cycle can only follow a program operation. table 4-2. erase block sizes blk1 blk0 block size, addresses cared 0 0 full array: 24 kbytes 0 1 one-half array: 16 kbytes (a14 ) 1 0 eight rows: 512 bytes (a14?a9) 1 1 single row: 64 bytes (a14?a6) flash memory mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor flash memory 63 to program and margin read the flash memory, use this step-by-step procedure: 1. set the pgm bit. this configur es the memory for program operation and enables the latchi ng of address and data for programming. 2. read from the blo ck protect register. 3. write data to the eight bytes of the page being programmed. this requires eight separat e write operations. 4. set the hven bit. 5. wait for a time, t prog . 6. clear the hven bit. 7. wait for a time, t hvtv . 8. set the margin bit. 9. wait for a time, t vtp . 10. clear the pgm bit. 11. wait for a time, t hvd . 12. read back data in verify mode. this is done in eight separate read operations which are each stretc hed by eight cycles. once the hven bit is set, the array cannot be read. 13. clear the margin bit. note: while these operations mu st be performed in th e order shown, other unrelated operations may o ccur between the steps. this program/margin read sequence is repeated th roughout the memory until all data is programm ed. for minimum overa ll programming time and least program disturb ef fect, the smart programming algorithm should be followed. (see 4.6 flash erase operation .) note: mask interrupts prior to setting hven. advance information mc68hc908mr24 ? rev. 4.1 64 flash memory freescale semiconductor flash memory figure 4-2. smart programming algorithm program flash initialize attempt counter set pgm bit and fdiv bits wait t hvtv wait t vtp set hven bit clear pgm bit set margin bit wait t hvd increment attempt counter y n to 0 y n programming operation failed programming operation complete write data to selected page wait t step clear hven bit margin read page of data clear margin bit margin read data equal to write data? attempt count equal to fls pulses ? read flash block smart programming algorithm page program/margin read procedure note: this page program algorithm assumes the page/s to be programmed are initially erased. note: this algorithm is mandatory for programming the flash. protect register flash memory mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor flash memory 65 4.8 flash block protection note: in performing a program or erase op eration, the flash block protect register must be read after setting the pg m or erase bit and before asserting the hven bit. due to the ability of the on-board charge pump to erase and program the flash memory in the target application, provision is made for protecting blocks of memory from unintentional erase or program operations due to system malfunction. this protection is done by reserving a location in the memory for block protect information and requiring that this location be read to enable setting of t he hven bit. when the bl ock protect register is read, its contents are latched by the flash control logic. if the address range for an erase or progra m operation includ es a protected block, the pgm or eras e bit is cleared which pr events the hven bit in the flash control regist er from being set so t hat no high voltage is allowed in the array. when the block protect regi ster is erased (all 0s), the entire memory is accessible for program an d erase. when bits wit hin the register are programmed, they lock blocks of memory address ranges as shown in 4.9 flash block pr otect register . the block protect re gister itself can be erased or programmed only wi th an external voltage, v hi , present on the irq pin. this voltage also allows entry from reset into the monitor mode. advance information mc68hc908mr24 ? rev. 4.1 66 flash memory freescale semiconductor flash memory 4.9 flash block protect register the block protect register is impl emented as a byte within the flash memory. each bit, when programmed, protects a range of addresses in the flash. bpr3 ? block protec t register bit 3 this bit protects the memory contents in the address range $f000?$ffff. 1 = address range protect ed from erase or program 0 = address range open to erase or program bpr2 ? block protec t register bit 2 this bit protects the memory contents in the address range $e000?$ffff. 1 = address range protect ed from erase or program 0 = address range open to erase or program bpr1 ? block protec t register bit 1 this bit protects the memory contents in the address range $c000?$ffff. 1 = address range protect ed from erase or program 0 = address range open to erase or program address: $ff80 bit 7654321bit 0 read: 0000 bpr3 bpr2 bpr1 bpr0 write: reset:00000000 = unimplemented figure 4-3. flash block pr otect register (flbpr) flash memory mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor flash memory 67 bpr0 ? block protec t register bit 0 this bit protects the memory contents in the address range $a000?$ffff. 1 = address range protect ed from erase or program 0 = address range open to erase or program by programming the block protect bi ts, a portion of th e memory will be locked so that no further eras e or program operations may be performed. programming more than one bit at a time is redundant. if both bit 1 and bit 2 are set, for instance, the ad dress range $c000 through $ffff is locked. if all bits are erased, t hen all of the memory is available for erase and program . the presence of a voltage + v hi on the irq pin will bypass the block protection so that all of the memory, including the block protect regist er, is open for program and erase operations. 4.10 wait mode putting the mcu into wa it mode while the flash is in read mode does not affect the operation of the flash me mory directly, bu t there will not be any memory activity si nce the cpu is inactive. the wait instruction should not be executed while performing a program or erase operat ion on the flash. when the mcu is put into wait mode, the charge pump for the fla sh is disabled so that either a program or erase operation will not continue. if t he memory is in either program mode (pgm = 1, hven = 1) or er ase mode (erase = 1, hven = 1), then it will remain in that mode during wait. exit from wait must now be done with a re set rather than an interr upt because if exiting wait with an interrupt, the memory will not be in read mode and the interrupt vector cannot be read from the memory. advance information mc68hc908mr24 ? rev. 4.1 68 flash memory freescale semiconductor flash memory mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor configuration register (config) 69 advance information ? mc68hc908mr24 section 5. configuration register (config) 5.1 contents 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 5.2 introduction this section describe s the configuration register (config). this register contains bits that co nfigure these options: resets caused by the low-vo ltage inhibit (lvi) module power to the lvi module computer operating pr operly (cop) module top-side pulse-width m odulator (pwm) polarity bottom-side pwm polarity edge-aligned versus center-aligned pwms six independent pwms versus th ree complementary pwm pairs advance information mc68hc908mr24 ? rev. 4.1 70 configuration register (config) freescale semiconductor configuration register (config) 5.3 functional description the configuration register (config) is used in the initialization of various options. the configuration r egister can be writ ten once after each reset. all of the conf iguration register bits are cleared during reset. since the various options affect the operation of th e mcu, it is recommended that this register be wr itten immediately after reset. the configuration register is located at $001f and may be read at anytime. note: on a flash device, the options are one-time writeable by the user after each reset. the registers are not in the flash memory but are special registers containing one- time writeable latches after each reset. upon a reset, the configuration register defaults to pr edetermined settings as shown in figure 5-1 . if the lvi module and the lvi rese t signal are enabled, a reset occurs when v dd falls to a voltage, v lvrx , and remains at or be low that level for at least nine consecutive cpu cycl es. once an lvi reset occurs, the mcu remains in reset until v dd rises to a voltage, v lvrx . edge ? edge- align enable bit edge determines if the motor control pwm will operate in edge-aligned mode or cent er-aligned mode. see section 9. pulse-width modulator fo r motor control (pwmmc) . 1 = edge-aligned mode enabled 0 = center-alig ned mode enabled address: $001f bit 7654321bit 0 read: edge botneg topneg indep lvirst lvipwr bit 1 copd write: reset:00001100 figure 5-1. configurat ion register (config) configuration register (config) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor configuration register (config) 71 botneg ? bottom-si de pwm polarity bit botneg determines if the bottom- side pwms will have positive or negative polarity. see section 9. pulse-widt h modulator for motor control (pwmmc) . 1 = negative polarity 0 = positive polarity topneg ? top-side pwm polarity bit topneg determines if the top-si de pwms will have positive or negative polarity. see section 9. pulse-widt h modulator for motor control (pwmmc) . 1 = negative polarity 0 = positive polarity indep ? independent mode enable bit indep determines if t he motor control pwms will be six independent pwms or three complem entary pwm pairs. see section 9. pulse-width modulator fo r motor control (pwmmc) . 1 = six independent pwms 0 = three complementary pwm pairs lvirst ? lvi reset enable bit lvirst enables the reset si gnal from the lvi module. see section 18. low-volt age inhibit (lvi) . 1 = lvi module resets enabled 0 = lvi module resets disabled lvipwr ? lvi power enable bit lvipwr enables the lvi module. see section 18. low-voltage inhibit (lvi) . 1 = lvi module power enabled 0 = lvi module power disabled bit 1 writing a 0 or a 1 to bit 1 has no effect on mcu operation. bit 1 operates the same as th e other bits within th is write-once register operate. advance information mc68hc908mr24 ? rev. 4.1 72 configuration register (config) freescale semiconductor configuration register (config) copd ? cop disable bit copd disables the cop module. see section 16. computer operating properly (cop) . 1 = cop module disabled 0 = cop module enabled mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor central processor unit (cpu) 73 advance information ? mc68hc908mr24 section 6. central processor unit (cpu) 6.1 contents 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.4 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.4.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.4.2 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.4.3 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.4.4 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.4.5 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.5 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.6 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.7 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.2 introduction this section describes the central processor unit (cpu08, version a). the m68hc08 cpu is an enhanced and fully object-code-compatible version of the m68hc05 cpu. the cpu08 reference manual , freescale document order numb er cpu08rm/ad, contains a description of the cpu instruct ion set, addressing modes, and architecture. advance information mc68hc908mr24 ? rev. 4.1 74 central processor unit (c pu) freescale semiconductor central processor unit (cpu) 6.3 features features of the cpu include: fully upward, object-code com patibility with m68hc05 family 16-bit stack pointer with st ack manipulation instructions 16-bit index register with x-re gister manipulation instructions 8-mhz cpu internal bus frequency 64-kbyte program/data memory space 16 addressing modes memory-to-memory data moves without using accumulator fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions enhanced binary-coded decim al (bcd) data handling modular architecture with exp andable internal bu s definition for extension of addressi ng range beyond 64 kbytes low-power wait mode 6.4 cpu registers figure 6-1 shows the five cpu registers. cpu regist ers are not part of the memory map. central processor unit (cpu) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor central processor unit (cpu) 75 figure 6-1. cpu registers 6.4.1 accumulator the accumulator is a general-purpose 8- bit register. the cpu uses the accumulator to hold operands and th e results of arithmetic/logic operations. accumulator (a) index register (h:x) stack pointer (sp) program counter (pc) condition code register (ccr) carry/borrow flag zero flag negative flag interrupt mask half-carry flag two?s complement overflow flag v11hinzc h x 0 0 0 0 7 15 15 15 70 bit 7654321bit 0 read: write: reset: unaffected by reset figure 6-2. accumulator (a) advance information mc68hc908mr24 ? rev. 4.1 76 central processor unit (c pu) freescale semiconductor central processor unit (cpu) 6.4.2 index register the 16-bit index register allows indexed addressing of a 64-kbyte memory space. h is the upper byte of the index regi ster, and x is the lower byte. h:x is the conc atenated 16-bit index register. in the indexed addressi ng modes, the cpu uses the contents of the index register to determine the conditional addr ess of the operand. the index register can serve also as a temporary data storage location. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 bit 0 read: write: reset:0 0 0 0 0 0 0 0xxxxxxxx x = indeterminate figure 6-3. index register (h:x) central processor unit (cpu) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor central processor unit (cpu) 77 6.4.3 stack pointer the stack pointer is a 16-bi t register that contains the address of the next location on the stack. during a rese t, the stack pointer is preset to $00ff. the reset stack pointer (rsp ) instruction sets the least significant byte to $ff and does not af fect the most significant byte. the stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. in the stack pointer 8-bi t offset and 16-bit offs et addressing modes, the stack pointer can functi on as an index register to access data on the stack. the cpu uses the contents of the stack pointer to determine the conditional address of the operand. note: the location of the stack is arbitr ary and may be relocated anywhere in ram. moving the sp out of p age zero ($0000?$00ff) frees direct address (page zero) space. for correct operation, the stack pointer must point only to ram locations. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 bit 0 read: write: reset:0000000011111111 figure 6-4. stack pointer (sp) advance information mc68hc908mr24 ? rev. 4.1 78 central processor unit (c pu) freescale semiconductor central processor unit (cpu) 6.4.4 program counter the program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. normally, the program counter autom atically increm ents to the next sequential memory location every time an instruct ion or operand is fetched. jump, branch, and interr upt operations l oad the program counter with an addr ess other than that of the next sequential location. during reset, the program counter is loaded with the reset vector address located at $fffe and $ffff. the vect or address is the address of the first instruction to be executed after exiti ng the reset state. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 bit 0 read: write: reset: loaded with vector from $fffe and $ffff figure 6-5. prog ram counter (pc) central processor unit (cpu) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor central processor unit (cpu) 79 6.4.5 condition code register the 8-bit condition code register cont ains the interrupt mask and five flags that indicate the re sults of the instruction just executed. bits 6 and 5 are set permanently to logic 1. the functions of the condition code register are described here. v ? overflow flag the cpu sets the overfl ow flag when a two's complement overflow occurs. the signed branch instructions bgt, bge, ble, and blt use the overflow flag. 1 = overflow 0 = no overflow h ? half-carry flag the cpu sets the half-carry fl ag when a carry occurs between accumulator bits 3 and 4 during an add or adc o peration. the half- carry flag is required for binary- coded decimal (bcd ) arithmetic operations. the daa instru ction uses the states of the h and c flags to determine the appropriate correction factor. 1 = carry between bits 3 and 4 0 = no carry between bits 3 and 4 bit 76 5 4 3 2 1bit 0 read: v11hinzc write: reset:x11x1xxx x = indeterminate figure 6-6. condition code register (ccr) advance information mc68hc908mr24 ? rev. 4.1 80 central processor unit (c pu) freescale semiconductor central processor unit (cpu) i ? interrupt mask bit when the interrupt mask is set, all maskable cpu interrupts are disabled. cpu interrupts are ena bled when the interrupt mask is cleared. when a cpu in terrupt occurs, the interrupt mask is set automatically after t he cpu registers are sa ved on the stack, but before the interrupt vector is fetched. 1 = interrupts disabled 0 = interrupts enabled note: to maintain m6805 compatibility, the upper byte of the i ndex register (h) is not stacked automatical ly. if the interrupt serv ice routine modifies h, then the user must st ack and unstack h using the pshh and pulh instructions. after the i bit is clear ed, the highest-priority interrupt request is serviced first. a return-from-interrupt (rti) instru ction pulls the cpu registers from the stack and restores the interr upt mask from the stack. after any reset, the interrupt mask is set and can be cleared only by the clear interrupt mask software instruction (cli). n ? negative flag the cpu sets the negative flag when an arithmet ic operation, logic operation, or data manipulation pr oduces a negative result, setting bit 7 of the result. 1 = negative result 0 = non-negative result z ? zero flag the cpu sets the zero flag when an arithmetic operation, logic operation, or data manipulati on produces a result of $00. 1 = zero result 0 = non-zero result central processor unit (cpu) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor central processor unit (cpu) 81 c ? carry/borrow flag the cpu sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of th e accumulator or when a subtraction operation requires a borrow. some instructions ? such as bit test and branch, shift, and rotate ? also clear or set the carry/borrow flag. 1 = carry out of bit 7 0 = no carry out of bit 7 6.5 arithmetic/logic unit (alu) the alu performs the arit hmetic and logic operat ions defined by the instruction set. refer to the cpu08 reference manual, freescale document order number cpu08rm/ad, for a descripti on of the instructions and addressing modes and more det ail about cpu architecture. advance information mc68hc908mr24 ? rev. 4.1 82 central processor unit (c pu) freescale semiconductor central processor unit (cpu) 6.6 instruction set summary table 6-1 provides a summary of t he m68hc08 instruction set. table 6-1. instruction se t summary (sheet 1 of 8) source form operation description effect on ccr address mode opcode operand cycles vh i nzc adc # opr adc opr adc opr adc opr ,x adc opr ,x adc ,x adc opr ,sp adc opr ,sp add with carry a (a) + (m) + (c) ?? ? ??? imm dir ext ix2 ix1 ix sp1 sp2 a9 b9 c9 d9 e9 f9 9ee9 9ed9 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 add # opr add opr add opr add opr ,x add opr ,x add ,x add opr ,sp add opr ,sp add without carry a (a) + (m) ?? ? ??? imm dir ext ix2 ix1 ix sp1 sp2 ab bb cb db eb fb 9eeb 9edb ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ais # opr add immediate value (signed) to sp sp (sp) + (16 ? m) ??????imm a7 ii 2 aix # opr add immediate value (signed) to h:x h:x (h:x) + (16 ? m) ??????imm af ii 2 and # opr and opr and opr and opr ,x and opr ,x and ,x and opr ,sp and opr ,sp logical and a (a) & (m) 0 ? ? ?? ? imm dir ext ix2 ix1 ix sp1 sp2 a4 b4 c4 d4 e4 f4 9ee4 9ed4 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 asl opr asla aslx asl opr ,x asl ,x asl opr ,sp arithmetic shift left (same as lsl) ? ?? ??? dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 asr opr asra asrx asr opr ,x asr opr ,x asr opr ,sp arithmetic shift right ? ?? ??? dir inh inh ix1 ix sp1 37 47 57 67 77 9e67 dd ff ff 4 1 1 4 3 5 bcc rel branch if carry bit clear pc (pc) + 2 + rel ? (c) = 0 ??????rel 24 rr 3 c b0 b7 0 b0 b7 c central processor unit (cpu) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor central processor unit (cpu) 83 bclr n , opr clear bit n in m mn 0 ?????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 bcs rel branch if carry bit set (same as blo) pc (pc) + 2 + rel ? (c) = 1 ??????rel 25 rr 3 beq rel branch if equal pc (pc) + 2 + rel ? (z) = 1 ??????rel 27 rr 3 bge opr branch if greater than or equal to (signed operands) pc (pc) + 2 + rel ? (n v ) = 0 ??????rel 90 rr 3 bgt opr branch if greater than (signed operands) pc (pc) + 2 + rel ? (z) | (n v ) = 0 ??????rel 92 rr 3 bhcc rel branch if half carry bit clear pc (pc) + 2 + rel ? (h) = 0 ??????rel 28 rr 3 bhcs rel branch if half carry bit set pc (pc) + 2 + rel ? (h) = 1 ??????rel 29 rr 3 bhi rel branch if higher pc (pc) + 2 + rel ? (c) | (z) = 0 ??????rel 22 rr 3 bhs rel branch if higher or same (same as bcc) pc (pc) + 2 + rel ? (c) = 0 ??????rel 24 rr 3 bih rel branch if irq pin high pc (pc) + 2 + rel ? irq = 1 ??????rel 2f rr 3 bil rel branch if irq pin low pc (pc) + 2 + rel ? irq = 0 ??????rel 2e rr 3 bit # opr bit opr bit opr bit opr ,x bit opr ,x bit ,x bit opr ,sp bit opr ,sp bit test (a) & (m) 0 ? ? ?? ? imm dir ext ix2 ix1 ix sp1 sp2 a5 b5 c5 d5 e5 f5 9ee5 9ed5 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ble opr branch if less than or equal to (signed operands) pc (pc) + 2 + rel ? (z) | (n v ) = 1 ??????rel 93 rr 3 blo rel branch if lower (same as bcs) pc (pc) + 2 + rel ? (c) = 1 ??????rel 25 rr 3 bls rel branch if lower or same pc (pc) + 2 + rel ? (c) | (z) = 1 ??????rel 23 rr 3 blt opr branch if less than (signed operands) pc (pc) + 2 + rel ? (n v ) = 1 ??????rel 91 rr 3 bmc rel branch if interrupt mask clear pc (pc) + 2 + rel ? (i) = 0 ??????rel 2c rr 3 bmi rel branch if minus pc (pc) + 2 + rel ? (n) = 1 ??????rel 2b rr 3 bms rel branch if interrupt mask set pc (pc) + 2 + rel ? (i) = 1 ??????rel 2d rr 3 table 6-1. instruction se t summary (sheet 2 of 8) source form operation description effect on ccr address mode opcode operand cycles vh i nzc advance information mc68hc908mr24 ? rev. 4.1 84 central processor unit (c pu) freescale semiconductor central processor unit (cpu) bne rel branch if not equal pc (pc) + 2 + rel ? (z) = 0 ??????rel 26 rr 3 bpl rel branch if plus pc (pc) + 2 + rel ? (n) = 0 ??????rel 2a rr 3 bra rel branch always pc (pc) + 2 + rel ??????rel 20 rr 3 brclr n , opr , rel branch if bit n in m clear pc (pc) + 3 + rel ? (mn) = 0 ????? ? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc (pc) + 2 ??????rel 21 rr 3 brset n , opr , rel branch if bit n in m set pc (pc) + 3 + rel ? (mn) = 1 ????? ? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 bset n , opr set bit n in m mn 1 ?????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 bsr rel branch to subroutine pc (pc) + 2; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1 pc (pc) + rel ??????rel ad rr 4 cbeq opr,rel cbeqa # opr,rel cbeqx # opr,rel cbeq opr, x+ ,rel cbeq x+ ,rel cbeq opr, sp ,rel compare and branch if equal pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 3 + rel ? (x) ? (m) = $00 pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 2 + rel ? (a) ? (m) = $00 pc (pc) + 4 + rel ? (a) ? (m) = $00 ?????? dir imm imm ix1+ ix+ sp1 31 41 51 61 71 9e61 dd rr ii rr ii rr ff rr rr ff rr 5 4 4 5 4 6 clc clear carry bit c 0 ?????0inh 98 1 cli clear interrupt mask i 0 ??0???inh 9a 2 clr opr clra clrx clrh clr opr ,x clr ,x clr opr ,sp clear m $00 a $00 x $00 h $00 m $00 m $00 m $00 0??01? dir inh inh inh ix1 ix sp1 3f 4f 5f 8c 6f 7f 9e6f dd ff ff 3 1 1 1 3 2 4 table 6-1. instruction se t summary (sheet 3 of 8) source form operation description effect on ccr address mode opcode operand cycles vh i nzc central processor unit (cpu) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor central processor unit (cpu) 85 cmp # opr cmp opr cmp opr cmp opr ,x cmp opr ,x cmp ,x cmp opr ,sp cmp opr ,sp compare a with m (a) ? (m) ? ?? ??? imm dir ext ix2 ix1 ix sp1 sp2 a1 b1 c1 d1 e1 f1 9ee1 9ed1 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 com opr coma comx com opr ,x com ,x com opr ,sp complement (one?s complement) m (m ) = $ff ? (m) a (a ) = $ff ? (m) x (x ) = $ff ? (m) m (m ) = $ff ? (m) m (m ) = $ff ? (m) m (m ) = $ff ? (m) 0?? ?? 1 dir inh inh ix1 ix sp1 33 43 53 63 73 9e63 dd ff ff 4 1 1 4 3 5 cphx # opr cphx opr compare h:x with m (h:x) ? (m:m + 1) ? ?? ??? imm dir 65 75 ii ii+1 dd 3 4 cpx # opr cpx opr cpx opr cpx ,x cpx opr ,x cpx opr ,x cpx opr ,sp cpx opr ,sp compare x with m (x) ? (m) ? ?? ??? imm dir ext ix2 ix1 ix sp1 sp2 a3 b3 c3 d3 e3 f3 9ee3 9ed3 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 daa decimal adjust a (a) 10 u?? ??? inh 72 2 dbnz opr,rel dbnza rel dbnzx rel dbnz opr, x ,rel dbnz x ,rel dbnz opr, sp ,rel decrement and branch if not zero a (a) ? 1 or m (m) ? 1 or x (x) ? 1 pc (pc) + 3 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 3 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 4 + rel ? (result) 0 ?????? dir inh inh ix1 ix sp1 3b 4b 5b 6b 7b 9e6b dd rr rr rr ff rr rr ff rr 5 3 3 5 4 6 dec opr deca decx dec opr ,x dec ,x dec opr ,sp decrement m (m) ? 1 a (a) ? 1 x (x) ? 1 m (m) ? 1 m (m) ? 1 m (m) ? 1 ? ?? ?? ? dir inh inh ix1 ix sp1 3a 4a 5a 6a 7a 9e6a dd ff ff 4 1 1 4 3 5 div divide a (h:a)/(x) h remainder ???? ?? inh 52 7 eor # opr eor opr eor opr eor opr ,x eor opr ,x eor ,x eor opr ,sp eor opr ,sp exclusive or m with a a (a m) 0?? ?? ? imm dir ext ix2 ix1 ix sp1 sp2 a8 b8 c8 d8 e8 f8 9ee8 9ed8 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 table 6-1. instruction se t summary (sheet 4 of 8) source form operation description effect on ccr address mode opcode operand cycles vh i nzc advance information mc68hc908mr24 ? rev. 4.1 86 central processor unit (c pu) freescale semiconductor central processor unit (cpu) inc opr inca incx inc opr ,x inc ,x inc opr ,sp increment m (m) + 1 a (a) + 1 x (x) + 1 m (m) + 1 m (m) + 1 m (m) + 1 ? ?? ?? ? dir inh inh ix1 ix sp1 3c 4c 5c 6c 7c 9e6c dd ff ff 4 1 1 4 3 5 jmp opr jmp opr jmp opr ,x jmp opr ,x jmp ,x jump pc jump address ?????? dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 2 3 4 3 2 jsr opr jsr opr jsr opr ,x jsr opr ,x jsr ,x jump to subroutine pc (pc) + n ( n = 1, 2, or 3) push (pcl); sp (sp) ? 1 push (pch); sp (sp) ? 1 pc unconditional address ?????? dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 4 5 6 5 4 lda # opr lda opr lda opr lda opr ,x lda opr ,x lda ,x lda opr ,sp lda opr ,sp load a from m a (m) 0?? ?? ? imm dir ext ix2 ix1 ix sp1 sp2 a6 b6 c6 d6 e6 f6 9ee6 9ed6 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ldhx # opr ldhx opr load h:x from m h:x ( m:m + 1 ) 0?? ?? ? imm dir 45 55 ii jj dd 3 4 ldx # opr ldx opr ldx opr ldx opr ,x ldx opr ,x ldx ,x ldx opr ,sp ldx opr ,sp load x from m x (m) 0?? ?? ? imm dir ext ix2 ix1 ix sp1 sp2 ae be ce de ee fe 9eee 9ede ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 lsl opr lsla lslx lsl opr ,x lsl ,x lsl opr ,sp logical shift left (same as asl) ? ?? ??? dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 lsr opr lsra lsr x lsr opr ,x lsr ,x lsr opr ,sp logical shift right ? ??0 ?? dir inh inh ix1 ix sp1 34 44 54 64 74 9e64 dd ff ff 4 1 1 4 3 5 mov opr,opr mov opr, x+ mov # opr,opr mov x+ ,opr move (m) destination (m) source h:x (h:x) + 1 (ix+d, dix+) 0?? ?? ? dd dix+ imd ix+d 4e 5e 6e 7e dd dd dd ii dd dd 5 4 4 4 mul unsigned multiply x:a (x) (a) ?0???0inh 42 5 table 6-1. instruction se t summary (sheet 5 of 8) source form operation description effect on ccr address mode opcode operand cycles vh i nzc c b0 b7 0 b0 b7 c 0 central processor unit (cpu) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor central processor unit (cpu) 87 neg opr nega negx neg opr ,x neg ,x neg opr ,sp negate (two?s complement) m ?(m) = $00 ? (m) a ?(a) = $00 ? (a) x ?(x) = $00 ? (x) m ?(m) = $00 ? (m) m ?(m) = $00 ? (m) ? ?? ??? dir inh inh ix1 ix sp1 30 40 50 60 70 9e60 dd ff ff 4 1 1 4 3 5 nop no operation none ??????inh 9d 1 nsa nibble swap a a (a[3:0]:a[7:4]) ??????inh 62 3 ora # opr ora opr ora opr ora opr ,x ora opr ,x ora ,x ora opr ,sp ora opr ,sp inclusive or a and m a (a) | (m) 0 ? ? ?? ? imm dir ext ix2 ix1 ix sp1 sp2 aa ba ca da ea fa 9eea 9eda ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 psha push a onto stack push (a); sp (sp ) ? 1 ??????inh 87 2 pshh push h onto stack push (h) ; sp (sp ) ? 1 ??????inh 8b 2 pshx push x onto stack push (x) ; sp (sp ) ? 1 ??????inh 89 2 pula pull a from stack sp (sp + 1); pull ( a ) ??????inh 86 2 pulh pull h from stack sp (sp + 1); pull ( h ) ??????inh 8a 2 pulx pull x from stack sp (sp + 1); pull ( x ) ??????inh 88 2 rol opr rola rolx rol opr ,x rol ,x rol opr ,sp rotate left through carry ? ?? ??? dir inh inh ix1 ix sp1 39 49 59 69 79 9e69 dd ff ff 4 1 1 4 3 5 ror opr rora rorx ror opr ,x ror ,x ror opr ,sp rotate right through carry ? ?? ??? dir inh inh ix1 ix sp1 36 46 56 66 76 9e66 dd ff ff 4 1 1 4 3 5 rsp reset stack pointer sp $ff ??????inh 9c 1 rti return from interrupt sp (sp) + 1; pull (ccr) sp (sp) + 1; pull (a) sp (sp) + 1; pull (x) sp (sp) + 1; pull (pch) sp (sp) + 1; pull (pcl) ?????? inh 80 7 rts return from subroutine sp sp + 1 ; pull ( pch) sp sp + 1; pull (pcl) ??????inh 81 4 table 6-1. instruction se t summary (sheet 6 of 8) source form operation description effect on ccr address mode opcode operand cycles vh i nzc c b0 b7 b0 b7 c advance information mc68hc908mr24 ? rev. 4.1 88 central processor unit (c pu) freescale semiconductor central processor unit (cpu) sbc # opr sbc opr sbc opr sbc opr ,x sbc opr ,x sbc ,x sbc opr ,sp sbc opr ,sp subtract with carry a (a) ? (m) ? (c) ? ?? ??? imm dir ext ix2 ix1 ix sp1 sp2 a2 b2 c2 d2 e2 f2 9ee2 9ed2 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 sec set carry bit c 1 ?????1inh 99 1 sei set interrupt mask i 1 ??1???inh 9b 2 sta opr sta opr sta opr ,x sta opr ,x sta ,x sta opr ,sp sta opr ,sp store a in m m (a) 0?? ?? ? dir ext ix2 ix1 ix sp1 sp2 b7 c7 d7 e7 f7 9ee7 9ed7 dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sthx opr store h:x in m (m:m + 1) (h:x) 0 ? ? ?? ? dir 35 dd 4 stop enable irq pin; stop oscillator i 0; stop oscillator ??0???inh 8e 1 stx opr stx opr stx opr ,x stx opr ,x stx ,x stx opr ,sp stx opr ,sp store x in m m (x) 0?? ?? ? dir ext ix2 ix1 ix sp1 sp2 bf cf df ef ff 9eef 9edf dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sub # opr sub opr sub opr sub opr ,x sub opr ,x sub ,x sub opr ,sp sub opr ,sp subtract a (a) ? (m) ? ?? ??? imm dir ext ix2 ix1 ix sp1 sp2 a0 b0 c0 d0 e0 f0 9ee0 9ed0 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 swi software interrupt pc (pc) + 1; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1; push (x) sp (sp) ? 1; push (a) sp (sp) ? 1; push (ccr) sp (sp) ? 1; i 1 pch interrupt vector high byte pcl interrupt vector low byte ??1???inh 83 9 tap transfer a to ccr ccr (a) ?????? inh 84 2 tax transfer a to x x (a) ??????inh 97 1 tpa transfer ccr to a a (ccr) ??????inh 85 1 table 6-1. instruction se t summary (sheet 7 of 8) source form operation description effect on ccr address mode opcode operand cycles vh i nzc central processor unit (cpu) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor central processor unit (cpu) 89 6.7 opcode map see table 6-2 . tst opr tsta tstx tst opr ,x tst ,x tst opr ,sp test for negative or zero (a) ? $00 or (x) ? $00 or (m) ? $00 0 ? ? ?? ? dir inh inh ix1 ix sp1 3d 4d 5d 6d 7d 9e6d dd ff ff 3 1 1 3 2 4 tsx transfer sp to h:x h:x (sp) + 1 ??????inh 95 2 txa transfer x to a a (x) ??????inh 9f 1 txs transfer h:x to sp (sp) (h:x) ? 1 ??????inh 94 2 wait enable interrupts; stop processor i bit 0 ??0???inh 8f 1 a accumulator n any bit c carry/borrow bit opr operand (one or two bytes) ccr condition code register pc program counter dd direct address of operand pch program counter high byte dd rr direct address of operand and relative offset of branch instruction pcl program counter low byte dd direct to direct addressing mode rel relative addressing mode dir direct addressing mode rel relative program counter offset byte dix+ direct to indexed with pos t increment addressing mode rr relati ve program counter offset byte ee ff high and low bytes of offset in indexed, 16-bit offs et addressing sp1 stack pointer , 8-bit offset addressing mode ext extended addressing mode sp2 stack pointer 16-bit offset addressing mode ff offset byte in indexed, 8-bit offset addressing sp stack pointer h half-carry bit u undefined h index register high byte v overflow bit hh ll high and low bytes of operand address in extended addressing x index register low byte i interrupt mask z zero bit ii immediate operand byte & logical and imd immediate source to direct des tination addressing mode | logical or imm immediate addressing mode logical exclusive or inh inherent addressing mode ( ) contents of ix indexed, no offset addressing mode ?( ) negation (two?s complement) ix+ indexed, no offset, post increment addressing mode # immediate value ix+d indexed with post increment to direct addressing mode ? sign extend ix1 indexed, 8-bit offset addressing mode loaded with ix1+ indexed, 8-bit offset, pos t increment addressing mode ? if ix2 indexed, 16-bit offset addressing mode : concatenated with m memory location ? set or cleared n negative bit ? not affected table 6-1. instruction se t summary (sheet 8 of 8) source form operation description effect on ccr address mode opcode operand cycles vh i nzc advance information mc68hc908mr24 ? rev. 4.1 90 central processor unit (cpu) freescale semiconductor central processor unit (cpu) table 6-2. opcode map bit manipulation branch read-modify-write control register/memory dir dir rel dir inh inh ix1 sp1 ix inh inh imm dir ext ix2 sp2 ix1 sp1 ix 0 1234569e6789abcd9ede9eef 0 5 brset0 3dir 4 bset0 2dir 3 bra 2rel 4 neg 2dir 1 nega 1inh 1 negx 1inh 4 neg 2ix1 5 neg 3sp1 3 neg 1ix 7 rti 1inh 3 bge 2rel 2 sub 2imm 3 sub 2dir 4 sub 3ext 4 sub 3ix2 5 sub 4sp2 3 sub 2ix1 4 sub 3sp1 2 sub 1ix 1 5 brclr0 3dir 4 bclr0 2dir 3 brn 2rel 5 cbeq 3dir 4 cbeqa 3imm 4 cbeqx 3imm 5 cbeq 3ix1+ 6 cbeq 4sp1 4 cbeq 2ix+ 4 rts 1inh 3 blt 2rel 2 cmp 2imm 3 cmp 2dir 4 cmp 3ext 4 cmp 3ix2 5 cmp 4sp2 3 cmp 2ix1 4 cmp 3sp1 2 cmp 1ix 2 5 brset1 3dir 4 bset1 2dir 3 bhi 2rel 5 mul 1inh 7 div 1inh 3 nsa 1inh 2 daa 1inh 3 bgt 2rel 2 sbc 2imm 3 sbc 2dir 4 sbc 3ext 4 sbc 3ix2 5 sbc 4sp2 3 sbc 2ix1 4 sbc 3sp1 2 sbc 1ix 3 5 brclr1 3dir 4 bclr1 2dir 3 bls 2rel 4 com 2dir 1 coma 1inh 1 comx 1inh 4 com 2ix1 5 com 3sp1 3 com 1ix 9 swi 1inh 3 ble 2rel 2 cpx 2imm 3 cpx 2dir 4 cpx 3ext 4 cpx 3ix2 5 cpx 4sp2 3 cpx 2ix1 4 cpx 3sp1 2 cpx 1ix 4 5 brset2 3dir 4 bset2 2dir 3 bcc 2rel 4 lsr 2dir 1 lsra 1inh 1 lsrx 1inh 4 lsr 2ix1 5 lsr 3sp1 3 lsr 1ix 2 ta p 1inh 2 txs 1inh 2 and 2imm 3 and 2dir 4 and 3ext 4 and 3ix2 5 and 4sp2 3 and 2ix1 4 and 3sp1 2 and 1ix 5 5 brclr2 3dir 4 bclr2 2dir 3 bcs 2rel 4 sthx 2dir 3 ldhx 3imm 4 ldhx 2dir 3 cphx 3imm 4 cphx 2dir 1 tpa 1inh 2 tsx 1inh 2 bit 2imm 3 bit 2dir 4 bit 3ext 4 bit 3ix2 5 bit 4sp2 3 bit 2ix1 4 bit 3sp1 2 bit 1ix 6 5 brset3 3dir 4 bset3 2dir 3 bne 2rel 4 ror 2dir 1 rora 1inh 1 rorx 1inh 4 ror 2ix1 5 ror 3sp1 3 ror 1ix 2 pula 1inh 2 lda 2imm 3 lda 2dir 4 lda 3ext 4 lda 3ix2 5 lda 4sp2 3 lda 2ix1 4 lda 3sp1 2 lda 1ix 7 5 brclr3 3dir 4 bclr3 2dir 3 beq 2rel 4 asr 2dir 1 asra 1inh 1 asrx 1inh 4 asr 2ix1 5 asr 3sp1 3 asr 1ix 2 psha 1inh 1 ta x 1inh 2 ais 2imm 3 sta 2dir 4 sta 3ext 4 sta 3ix2 5 sta 4sp2 3 sta 2ix1 4 sta 3sp1 2 sta 1ix 8 5 brset4 3dir 4 bset4 2dir 3 bhcc 2rel 4 lsl 2dir 1 lsla 1inh 1 lslx 1inh 4 lsl 2ix1 5 lsl 3sp1 3 lsl 1ix 2 pulx 1inh 1 clc 1inh 2 eor 2imm 3 eor 2dir 4 eor 3ext 4 eor 3ix2 5 eor 4sp2 3 eor 2ix1 4 eor 3sp1 2 eor 1ix 9 5 brclr4 3dir 4 bclr4 2dir 3 bhcs 2rel 4 rol 2dir 1 rola 1inh 1 rolx 1inh 4 rol 2ix1 5 rol 3sp1 3 rol 1ix 2 pshx 1inh 1 sec 1inh 2 adc 2imm 3 adc 2dir 4 adc 3ext 4 adc 3ix2 5 adc 4sp2 3 adc 2ix1 4 adc 3sp1 2 adc 1ix a 5 brset5 3dir 4 bset5 2dir 3 bpl 2rel 4 dec 2dir 1 deca 1inh 1 decx 1inh 4 dec 2ix1 5 dec 3sp1 3 dec 1ix 2 pulh 1inh 2 cli 1inh 2 ora 2imm 3 ora 2dir 4 ora 3ext 4 ora 3ix2 5 ora 4sp2 3 ora 2ix1 4 ora 3sp1 2 ora 1ix b 5 brclr5 3dir 4 bclr5 2dir 3 bmi 2rel 5 dbnz 3dir 3 dbnza 2inh 3 dbnzx 2inh 5 dbnz 3ix1 6 dbnz 4sp1 4 dbnz 2ix 2 pshh 1inh 2 sei 1inh 2 add 2imm 3 add 2dir 4 add 3ext 4 add 3ix2 5 add 4sp2 3 add 2ix1 4 add 3sp1 2 add 1ix c 5 brset6 3dir 4 bset6 2dir 3 bmc 2rel 4 inc 2dir 1 inca 1inh 1 incx 1inh 4 inc 2ix1 5 inc 3sp1 3 inc 1ix 1 clrh 1inh 1 rsp 1inh 2 jmp 2dir 3 jmp 3ext 4 jmp 3ix2 3 jmp 2ix1 2 jmp 1ix d 5 brclr6 3dir 4 bclr6 2dir 3 bms 2rel 3 tst 2dir 1 tsta 1inh 1 tstx 1inh 3 tst 2ix1 4 tst 3sp1 2 tst 1ix 1 nop 1inh 4 bsr 2rel 4 jsr 2dir 5 jsr 3ext 6 jsr 3ix2 5 jsr 2ix1 4 jsr 1ix e 5 brset7 3dir 4 bset7 2dir 3 bil 2rel 5 mov 3dd 4 mov 2dix+ 4 mov 3imd 4 mov 2ix+d 1 stop 1inh * 2 ldx 2imm 3 ldx 2dir 4 ldx 3ext 4 ldx 3ix2 5 ldx 4sp2 3 ldx 2ix1 4 ldx 3sp1 2 ldx 1ix f 5 brclr7 3dir 4 bclr7 2dir 3 bih 2rel 3 clr 2dir 1 clra 1inh 1 clrx 1inh 3 clr 2ix1 4 clr 3sp1 2 clr 1ix 1 wait 1inh 1 txa 1inh 2 aix 2imm 3 stx 2dir 4 stx 3ext 4 stx 3ix2 5 stx 4sp2 3 stx 2ix1 4 stx 3sp1 2 stx 1ix inh inherent rel relative sp1 stack pointer, 8-bit offset imm immediate ix indexed, no offset sp2 stack pointer, 16-bit offset dir direct ix1 indexed, 8-bit offset ix+ indexed, no offset with ext extended ix2 indexed, 16-bit offset post increment dd direct-direct imd immediate-direct ix1+ indexed, 1-byte offset with ix+d indexed-direct dix+ direct-indexed post increment * pre-byte for stack pointer indexed instructions 0 high byte of opcode in hexadecimal low byte of opcode in hexadecimal 0 5 brset0 3dir cycles opcode mnemonic number of bytes / addressing mode msb lsb msb lsb mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor system integration module (sim) 91 advance information ? mc68hc908mr24 section 7. system integration module (sim) 7.1 contents 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.3 sim bus clock control and generation . . . . . . . . . . . . . . . . . . 94 7.3.1 bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 7.3.2 clock startup from po r or lvi reset . . . . . . . . . . . . . . . . . 94 7.3.3 clocks in wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 7.4 reset and system initializa tion. . . . . . . . . . . . . . . . . . . . . . . . . 95 7.4.1 external pin reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.4.2 active resets from inte rnal sources . . . . . . . . . . . . . . . . . . 97 7.4.2.1 power-on reset (por) . . . . . . . . . . . . . . . . . . . . . . . . . . 98 7.4.2.2 computer operati ng properly (cop) reset. . . . . . . . . . . 99 7.4.2.3 illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 7.4.2.4 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 7.4.2.5 low-voltage inhibit (lvi) reset . . . . . . . . . . . . . . . . . . . 100 7.5 sim counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 7.5.1 sim counter during power-on rese t . . . . . . . . . . . . . . . . 100 7.5.2 sim counter and reset states. . . . . . . . . . . . . . . . . . . . . . 100 7.6 exception control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 7.6.1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 7.6.1.1 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 7.6.1.2 software interrupt (swi) instruction. . . . . . . . . . . . . . . . 104 7.6.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 7.7 low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 7.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 7.7.2 sim reset status regist er . . . . . . . . . . . . . . . . . . . . . . . . 107 advance information mc68hc908mr24 ? rev. 4.1 92 system integration module (sim) freescale semiconductor system integration module (sim) 7.2 introduction this section describes the system integration module (sim). together with the central processor unit (cpu), the sim controls all mcu activities. a block diagram of the sim is shown in figure 7-1 . the sim is a system state controller t hat coordinates cpu and exception timing. the sim is responsible for: bus clock generation and cont rol for cpu and peripherals: ? wait/reset/break entry and recovery ? internal clock control master reset control, incl uding power-on reset (por) and computer operating pr operly (cop) timeout interrupt control: ? acknowledge timing ? arbitration control timing ? vector address generation cpu enable/disable timing modular architecture exp andable to 128 interrupt sources table 7-1 shows the internal signal names used in this section. system integration module (sim) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor system integration module (sim) 93 figure 7-1. sim block diagram wait clock control clock generators por control reset pin control sim reset status register interrupt control and priority decode module wait cpu wait (from cpu) simoscen (to cgm) cgmout (from cgm) internal clocks master reset control reset pin logic lvi (from lvi module) illegal opcode (from cpu) illegal address (from address map decoders) cop (from cop module) interrupt sources cpu interface reset control sim counter cop clock cgmxclk (from cgm) 2 table 7-1. signal name conventions signal name description cgmxclk buffered version of osc1 from clock generator module (cgm) cgmvclk phase-locked loop (pll) circuit output cgmout pll-based or osc1-based clock output from cgm module (bus clock = cgmout divided by two) iab internal address bus idb internal data bus porrst signal from the power-on reset module to the sim irst internal reset signal r/w read/write signal advance information mc68hc908mr24 ? rev. 4.1 94 system integration module (sim) freescale semiconductor system integration module (sim) 7.3 sim bus clock control and generation the bus clock generator provides system clock signal s for the cpu and peripherals on the mcu. the syst em clocks are generated from an incoming clock, cg mout, as shown in figure 7-2 . this clock can come from either an external oscillator or from the on-chip phase-locked loop (pll) circuit. see section 8. clock g enerator module (cgm) . figure 7-2. cgm clock signals 7.3.1 bus timing in user mode , the internal bus fr equency is either t he crystal oscillator output (cgmxclk) divided by four or the pll output (cgmvclk) divided by four. see section 8. clock generator module (cgm) . 7.3.2 clock startup from por or lvi reset when the power-on reset (por) module or the low-voltage inhibit (lvi) module generates a reset, the clocks to the cpu and peripherals are inactive and held in an inactive phase until after the 4096 cgmxclk cycle por timeout has completed. the rst pin is driven low by the sim during this entire period. the inte rnal bus (ibus) clocks start upon completion of the timeout. pll osc1 cgmxclk 2 bus clock generators sim cgm sim counter ptc2 monitor mode clock select circuit cgmvclk bcs 2 a b s* cgmout *when s = 1, cgmout = b user mode system integration module (sim) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor system integration module (sim) 95 7.3.3 clocks in wait mode in wait mode, t he cpu clocks are inactive. th e sim also produces two sets of clocks for other modules. refer to the wait mode subsection of each module to see if t he module is active or i nactive in wait mode. some modules can be programmed to be active in wait mode. 7.4 reset and system initialization the mcu has these reset sources: power-on reset module (por) external reset pin (rst ) computer operating pr operly (cop) module low-voltage inhi bit (lvi) module illegal opcode illegal address all of these resets produce the vector $fffe?ffff ($fefe?feff in monitor mode) and assert the internal reset signal (irst). irst causes all registers to be returned to thei r default values and all modules to be returned to thei r reset states. an internal reset clear s the sim counter (see 7.5 sim counter ), but an external reset does not. each of th e resets sets a co rresponding bit in the sim reset status register (srsr). see 7.7.2 sim reset status register . advance information mc68hc908mr24 ? rev. 4.1 96 system integration module (sim) freescale semiconductor system integration module (sim) 7.4.1 external pin reset pulling the asynchronous rst pin low halts all pr ocessing. the pin bit of the sim reset status register (srsr) is set as long as rst is held low for a minimum of 67 cg mxclk cycles, assuming t hat neither the por nor the lvi was the sour ce of the reset. see table 7-2 for details. figure 7-3 shows the relative timing. figure 7-3. extern al reset timing table 7-2. pin bit set timing reset type number of cycl es required to set pin por/lvi 4163 (4096 + 64 + 3) all others 67 (64 + 3) rst iab pc vect h vect l cgmout system integration module (sim) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor system integration module (sim) 97 7.4.2 active resets from internal sources all internal reset sources actively pull the rst pin low for 32 cgmxclk cycles to allow resetting of exter nal peripherals. the internal reset signal (irst) continues to be asserted for an additional 32 cycles (see figure 7-4 ). an internal reset can be caused by an illegal address, illegal opcode, cop timeout, lv i, or por. (see figure 7-5 .) note: for lvi or por resets, the sim cycles through 4096 cgmxclk cycles during which the si m forces the rst pin low. the internal reset signal then follows the sequence fr om the falling edge of rst , as shown in figure 7-4 . figure 7-4. inter nal reset timing the cop reset is asynchro nous to the bus clock. figure 7-5. sources of internal reset the active reset feature allows the par t to issue a reset to peripherals and other chips within a system built around the mcu. irst rst rst pulled low by mcu iab 32 cycles 32 cycles vector high cgmxclk illegal address rst illegal opcode rst coprst lvi por internal reset advance information mc68hc908mr24 ? rev. 4.1 98 system integration module (sim) freescale semiconductor system integration module (sim) 7.4.2.1 power-on reset (por) when power is first applied to the mcu, the power-on reset (por) module generates a pulse to indicate that power on has occurred. the external reset pin (rst ) is held low while the sim counter counts out 4096 cgmxclk cycles. sixty-four cg mxclk cycles later, the cpu and memories are released from reset to allow the reset vector sequence to occur. at power on, thes e events occur: a por pulse is generated. the internal reset signal is asserted. the sim enables cgmout. internal clocks to the cpu and m odules are held i nactive for 4096 cgmxclk cycles to al low stabilization of the oscillator. the rst pin is driven low during th e oscillator stabilization time. the por bit of the sim reset status register (srsr) is set and all other bits in the register are cleared. figure 7-6. por recovery porrst osc1 cgmxclk cgmout rst iab 4096 cycles 32 cycles 32 cycles $fffe $ffff system integration module (sim) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor system integration module (sim) 99 7.4.2.2 computer operat ing properly (cop) reset an input to the sim is reserved for the cop reset signal. the overflow of the cop counter causes an internal reset and sets the cop bit in the sim reset status register (srsr). the sim actively pulls down the rst pin for all intern al reset sources. to prevent a cop module timeout, wr ite any value to location $ffff. writing to location $ffff clears t he cop counter and bits 12?4 of the sim counter. the sim counter output, which occu rs at least every 2 13 ? 2 4 cgmxclk cycles, drives the co p counter. the cop should be serviced as soon as possible out of reset to guarantee the maximum amount of time befor e the first timeout. the cop module is di sabled if the rst pin or the irq pin is held at v hi while the mcu is in monitor m ode. the cop modul e can be disabled only through combinational logic conditioned with the high voltage signal on the rst or the irq pin. this prevents t he cop from becoming disabled as a result of external noise. during a break state, v hi on the rst pin disables the cop module. 7.4.2.3 illegal opcode reset the sim decodes signals from the cpu to detect illegal instructions. an illegal instruction sets the ilop bi t in the sim reset status register (srsr) and causes a reset. because the mc68hc908mr 24 has stop mode dis abled, execution of the stop instruction will c ause an illegal opcode reset. 7.4.2.4 illegal address reset an opcode fetch from addresses other than flash or ram addresses generates an illegal address reset (unimplemented locations within memory map). the sim veri fies that the cpu is fetching an opcode prior to asserting the ilad bit in the si m reset status register (srsr) and resetting the mcu. a data fetch from an unmapped address does not generate a reset. advance information mc68hc908mr24 ? rev. 4.1 100 system integration module (sim) freescale semiconductor system integration module (sim) 7.4.2.5 low-voltage inhibit (lvi) reset the low-voltage inhibit (l vi) module asserts its output to the sim when the v dd voltage falls to the v lvrx voltage and remains at or below that level for at least nine c onsecutive cpu cycles (see 21.6 dc electrical characteristics (v dd = 5.0 vdc 10%) ). the lvi bit in the sim reset status register (srsr) is set, and the external reset pin (rst ) is held low while the sim counter counts out 4096 cgmxclk cycles. sixty-four cgmxclk cycles later, the cpu is released from re set to allow the reset vector sequence to occur. the sim actively pulls down the rst pin for all internal reset sources. 7.5 sim counter the sim counter is used by the power -on reset (por) module to allow the oscillator time to stabilize before enabling t he internal bus (ibus) clocks. the sim counter also serves as a prescaler for the computer operating properly (cop) module. the sim counter overflow supplies the clock for the cop module. the sim counter is 13 bits long and is clocked by the fall ing edge of cgmxclk. 7.5.1 sim counter during power-on reset the power-on reset (por) module dete cts power appli ed to the mcu. at power-on, the por ci rcuit asserts the signal porrst. once the sim is initialized, it enabl es the clock generation (c gm) module to drive the bus clock state machine. 7.5.2 sim counter and reset states external reset has no effect on the sim counter. the sim counter is free- running after all reset states. for counter con trol and internal reset recovery sequences, see 7.4.2 active resets fr om internal sources . system integration module (sim) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor system integration module (sim) 101 7.6 exception control normal, sequential progra m execution can be chang ed in three different ways: interrupts: ? maskable hardware cpu interrupts ? non-maskable software interrupt instruction (swi) reset break interrupts 7.6.1 interrupts at the beginning of an interrupt, the cpu sa ves the cpu register contents on the sta ck and sets the interrupt ma sk (i bit) to prevent additional interrupts. at the end of an interrupt, t he return-from-interrupt (rti) instruction recovers the cpu r egister contents from the stack so that normal processing can resume. figure 7-7 shows interrupt entry timing. figure 7-9 shows interrupt recovery timing. interrupts are latched, and arbitration is performed in the sim at the start of interrupt processing. the arbitration result is a constant that the cpu uses to determine which ve ctor to fetch. once an interrupt is latched by the sim, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serv iced (or the i bit is cleared). see figure 7-8 . figure 7-7 . interrupt entry module idb r/w interrupt dummy sp sp ? 1 sp ? 2 sp ? 3 sp ? 4 vect h vect l start addr iab dummy pc ? 1[7:0] pc ? 1[15:8] x a ccr v data h v data l opcode i bit advance information mc68hc908mr24 ? rev. 4.1 102 system integration module (sim) freescale semiconductor system integration module (sim) figure 7-8. interrupt processing no no yes as many interrupts as exist on chip swi instruction? rti instruction? fetch next instruction unstack cpu registers stack cpu registers set i bit load pc with interrupt vector execute instruction yes no yes no no yes i bit set? from reset break or swi i bit set? interrupt? yes interrupt? system integration module (sim) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor system integration module (sim) 103 figure 7-9. interrupt recovery 7.6.1.1 hardwa re interrupts a hardware interrupt does not stop the current in struction. processing of a hardware interrupt begins after completion of t he current instruction. when the current instruction is complete, the sim checks all pending hardware interrupts. if interrupts ar e not masked (i bit clear in the condition code register), and if the corres ponding interrupt enable bit is set, the sim proceeds with interrup t processing; other wise, the next instruction is fetched and executed. if more than one interrupt is pending at th e end of an instruction execution, the highest priority interrupt is serviced first. figure 7-10 demonstrates what hap pens when two interrupts are pending. if an interrupt is pending upon exit from the original inte rrupt service routine, the pending interrupt is serviced before the load-accumulator-from- memory (lda) instruction is executed. module idb r/w interrupt sp ? 4 sp ? 3 sp ? 2 sp ? 1 sp pc pc + 1 iab ccr a x pc ? 1[7:0] pc ? 1[15:8] opcode operand i bit advance information mc68hc908mr24 ? rev. 4.1 104 system integration module (sim) freescale semiconductor system integration module (sim) figure 7-10 . interrupt recognition example the lda opcode is pr efetched by both th e int1 and int2 rti instructions. however, in the case of the int1 rti prefetch, this is a redundant operation. note: to maintain compatibility with the m6805 family, the h register is not pushed on the stack during in terrupt entry. if the in terrupt service routine modifies the h register or uses the indexed addressing mode, software should save the h register and then restore it prio r to exiting the routine. 7.6.1.2 software inte rrupt (swi) instruction the software interrupt (swi) instruct ion is a non-maskable instruction that causes an interrupt regardless of the stat e of the interrupt mask (i bit) in the cond ition code register. 7.6.2 reset all reset sources always have equal and highest pr iority and cannot be arbitrated. cli lda int1 pulh rti int2 background routine #$ff pshh int1 interrupt service routine pulh rti pshh int2 interrupt service routine system integration module (sim) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor system integration module (sim) 105 7.7 low-power mode executing the wait instruction puts the mcu in a low power- consumption mode for st andby situations. the s im holds the cpu in a non-clocked state. wait clears the in terrupt mask (i) in the condition code register, allowing interrupts to occur. 7.7.1 wait mode in wait mode, t he cpu clocks are inactive while the peripheral clocks continue to run. figure 7-11 shows the timing fo r wait mode entry. a module that is active during wa it mode can wake up the cpu with an interrupt if the interrupt is enabled . stacking for the interrupt begins one cycle after the wait instruction dur ing which the inte rrupt occurred. refer to the wait mode su bsection of each module to see if the module is active or inactive in wait mode. some modules can be programmed to be active in wait mode. wait mode can also be exited by a reset. if the cop disable bit, copd, in the configuration r egister is logic 0, t hen the computer operating properly module (cop) is enabled and remains active in wait mode. figure 7-11. wait mode entry timing wait addr + 1 same same iab idb previous data next opcode same wait addr same r/w note: previous data can be operand data or the wait opcode, depending on the last instruction. advance information mc68hc908mr24 ? rev. 4.1 106 system integration module (sim) freescale semiconductor system integration module (sim) figure 7-12 and figure 7-13 show the timing for wait recovery. figure 7-12. wait re covery from interrupt figure 7-13. wait recover y from internal reset $6e0c $6e0b $00ff $00fe $00fd $00fc $a6 $a6 $01 $0b $6e $a6 iab idb exitstopwait note: exitstopwait = rst pin or cpu interrupt iab idb rst $a6 $a6 $6e0b rst vct h rst vct l $a6 cgmxclk 32 cycles 32 cycles system integration module (sim) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor system integration module (sim) 107 7.7.2 sim reset status register the sim reset status register (srsr) contains six flags that show the source of the last reset. clear the sim reset status register by reading it. a power-on reset sets the por bit and clears all other bits in the register. por ? power-on reset bit 1 = last reset caused by por circuit 0 = read of srsr pin ? external reset bit 1 = last reset caused by external reset pin (rst ) 0 = por or read of srsr cop ? computer operati ng properly reset bit 1 = last reset caused by cop counter 0 = por or read of srsr ilop ? illegal opcode reset bit 1 = last reset caused by an illegal opcode 0 = por or read of srsr ilad ? illegal address rese t bit (opcode fetches only) 1 = last reset caused by an opcode fetch from an illegal address 0 = por or read of srsr lvi ? low-voltage i nhibit reset bit 1 = last reset was caused by the lvi circuit 0 = por or read of srsr address: $fe01 bit 7654321bit 0 read: por pin cop ilop ilad 0 lvi 0 write: rrrrrrrr reset:10000000 r= reserved figure 7-14. sim reset status register (srsr) advance information mc68hc908mr24 ? rev. 4.1 108 system integration module (sim) freescale semiconductor system integration module (sim) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor clock generator module (cgm) 109 advance information ? mc68hc908mr24 section 8. clock generator module (cgm) 8.1 contents 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 8.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 8.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 8.4.1 crystal oscillator circ uit . . . . . . . . . . . . . . . . . . . . . . . . . . .111 8.4.2 phase-locked loop circ uit (pll) . . . . . . . . . . . . . . . . . . . 113 8.4.2.1 pll circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 8.4.2.2 acquisition and tracking modes . . . . . . . . . . . . . . . . . . 115 8.4.2.3 manual and automatic pll b andwidth modes . . . . . . . 115 8.4.2.4 programming the pll . . . . . . . . . . . . . . . . . . . . . . . . . . 117 8.4.2.5 special programming exceptions . . . . . . . . . . . . . . . . . 119 8.4.3 base clock selector ci rcuit . . . . . . . . . . . . . . . . . . . . . . . . 119 8.4.4 cgm external connectio ns . . . . . . . . . . . . . . . . . . . . . . . . 120 8.5 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 8.5.1 crystal amplifier input pin (osc1). . . . . . . . . . . . . . . . . . . 121 8.5.2 crystal amplifier ou tput pin (osc2) . . . . . . . . . . . . . . . . . 121 8.5.3 external filter capacitor pin (c gmxfc) . . . . . . . . . . . . . . 122 8.5.4 pll analog power pin (v dda ) . . . . . . . . . . . . . . . . . . . . . . 122 8.5.5 oscillator enable signal (simoscen). . . . . . . . . . . . . . . . 122 8.5.6 crystal output frequency signal (cgmxclk) . . . . . . . . . 122 8.5.7 cgm base clock output (cgmout) . . . . . . . . . . . . . . . . . 122 8.5.8 cgm cpu interrupt (cgmint) . . . . . . . . . . . . . . . . . . . . . 123 8.6 cgm registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 8.6.1 pll control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 8.6.2 pll bandwidth control register . . . . . . . . . . . . . . . . . . . . 126 8.6.3 pll programming regist er . . . . . . . . . . . . . . . . . . . . . . . . 128 8.7 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 8.8 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 advance information mc68hc908mr24 ? rev. 4.1 110 clock generator module (cgm) freescale semiconductor clock generator module (cgm) 8.9 acquisition/lock time spec ifications . . . . . . . . . . . . . . . . . . . 130 8.9.1 acquisition/lock time definitions. . . . . . . . . . . . . . . . . . . .130 8.9.2 parametric influences on reaction time . . . . . . . . . . . . . . 132 8.9.3 choosing a filter capac itor . . . . . . . . . . . . . . . . . . . . . . . . 133 8.9.4 reaction time calculat ion . . . . . . . . . . . . . . . . . . . . . . . . . 133 8.2 introduction this section describes the clock generator m odule (cgm, version a). the cgm generates the crystal clock si gnal, cgmxclk, which operates at the frequency of the crystal. the cgm also generates the base clock signal, cgmout, from which the system integration module (sim) derives the system clocks. cgmout is based on either the cryst al clock divided by two or the phase-locked loop (pll) cl ock, cgmvclk, divided by two. the pll is a frequency generator designed for us e with crystals or ceramic resonators. the pll can generate an 8-mhz bus frequency without using a 32-mhz external clock. 8.3 features features of the cgm include: pll with output frequen cy in integer multip les of the crystal reference programmable hardware voltage-c ontrolled oscillator (vco) for low-jitter operation automatic bandwidth control mode for low-jitt er operation automatic frequency lock detector central processor unit (cpu) interr upt on entry or exit from locked condition clock generator module (cgm) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor clock generator module (cgm) 111 8.4 functional description the cgm consists of three major submodules: crystal oscillator circuit ? the crystal osc illator circuit generates the constant crystal frequency clock, cgmxclk. phase-locked l oop (pll) ? the p ll generates the programmable vco frequen cy clock, cgmvclk. base clock selector circuit ? th is software-controlled circuit selects either cgmx clk divided by two or the vco clock, cgmvclk, divided by two as t he base clock, cgmout. the sim derives the system clocks from cgmout. figure 8-1 shows the struct ure of the cgm. 8.4.1 crystal os cillator circuit the crystal oscillator circuit consis ts of an inverting amplifier and an external crystal. the osc1 pin is t he input to the amp lifier and the osc2 pin is the output. the simoscen si gnal from the sys tem integration module (sim) enables the cr ystal oscillator circuit. the cgmxclk signal is t he output of the crystal oscillator circuit and runs at a rate equal to the crystal frequency. cg mxclk is then buffered to produce cgmrclk, t he pll reference clock. cgmxclk can be used by other modul es which require precise timing for operation. the duty cycle of cgmxclk is not guaranteed to be 50 percent and depends on external factors, in cluding the crystal and related exter nal components. an externally generated cl ock also can feed the os c1 pin of the crystal oscillator circuit. connect the exter nal clock to the o sc1 pin and let the osc2 pin float. advance information mc68hc908mr24 ? rev. 4.1 112 clock generator module (cgm) freescale semiconductor clock generator module (cgm) figure 8-1. cgm block diagram bcs phase detector loop filter frequency divider voltage controlled oscillator bandwidth control lock detector clock cgmxclk cgmout cgmvdv cgmvclk simoscen crystal oscillator interrupt control cgmint cgmrdv pll analog 3 2 cgmrclk select circuit lock auto acq vrs[7:4] pllie pllf mul[7:4] cgmxfc v ss v dda osc1 osc2 to sim to sim ptc2 monitor mode a b s* user mode *when s = 1, cgmout = b clock generator module (cgm) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor clock generator module (cgm) 113 8.4.2 phase-locked loop circuit (pll) the pll is a frequency gene rator that can operate in either acquisition mode or tracking mode, depending on the a ccuracy of the output frequency. the pll can change betw een acquisition and tracking modes either automat ically or manually. 8.4.2.1 pll circuits the pll consists of these circuits: voltage-controlled oscillator (vco) modulo vco fr equency divider phase detector loop filter lock detector addr. register name bit 7654321bit 0 $005c pll control register (pctl) see page 124. read: pllie pllf pllon bcs 1111 write: r r r r r reset:00101111 $005d pll bandwidth control register (pbwc) see page 126. read: auto lock acq xld 0000 write: r r r r r reset:00000000 $005e pll programming register (ppg) see page 128. read: mul7 mul6 mul5 mul4 vrs7 vrs6 vrs5 vrs4 write: reset:01100110 r=reserved figure 8-2. cgm i/o register summary advance information mc68hc908mr24 ? rev. 4.1 114 clock generator module (cgm) freescale semiconductor clock generator module (cgm) the operating range of the vco is programmable for a wide range of frequencies and for maximum immunity to external noise, including supply and cgmxfc noise. the vco frequency is bound to a range from roughly one-half to twice the center-of-range frequency, f vrs . modulating the voltage on the cg mxfc pin changes the frequency within this range. by design, f vrs is equal to the nom inal center-of-range frequency, f nom , (4.9152 mhz) times a linear factor, l or (l)f nom . cgmrclk is the pll reference clock, a buffered versio n of cgmxclk. cgmrclk runs at a frequency, f rclk , and is fed to t he pll through a buffer. the buffer output is the final reference cl ock, cgmrdv, running at a frequency f rdv =f rclk . the vco?s output clock, cgmvclk, running at a frequency f vclk , is fed back through a programmable modul o divider. the modulo divider reduces the vco clock by a factor, n. the divider?s out put is the vco feedback clock, cgmvdv, running at a frequency f vdv =f vclk /n. (see 8.4.2.4 programming the pll for more information.) the phase detector then compares th e vco feedback clock, cgmvdv, with the final reference clock, cgmrdv. a correction pulse is generated based on the phase di fference between the two si gnals. the loop filter then slightly alters t he dc voltage on the external capacitor connected to cgmxfc based on the wi dth and direction of th e correction pulse. the filter can make fa st or slow correcti ons depending on its mode, described in 8.4.2.2 acquisition and tracking modes . the value of the external capacitor and the refer ence frequency determines the speed of the corrections and the stability of the pll. the lock detector compares the freque ncies of the vco feedback clock, cgmvdv, and the final reference clock, cgmrdv. therefore, the speed of the lock detector is directly proportional to t he final reference frequency, f rdv . the circuit determines the mode of the pll and the lock condition based on this comparison. clock generator module (cgm) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor clock generator module (cgm) 115 8.4.2.2 acquisition and tracking modes the pll filter is manually or automatically conf igurable into one of two operating modes: 1. acquisition mode ? in acquisition m ode, the filter can make large frequency corrections to the vc o. this mode is used at pll startup or when the pll has su ffered a severe noise hit and the vco frequency is far off t he desired frequency. when in acquisition mode, the acq bit is clear in the pll bandwidth control register. (see 8.6.2 pll bandwidth control register .) 2. tracking mode ? in tr acking mode, the filt er makes only small corrections to the frequency of t he vco. pll jitter is much lower in tracking mode, but the response to noise is also slower. the pll enters tracking mode wh en the vco frequency is nearly correct, such as when the pll is selected as the base clock source. (see 8.4.3 base clock se lector circuit .) the pll is automatically in tracking mode wh en not in acqui sition mode or when the acq bit is set. 8.4.2.3 manual and automa tic pll bandwidth modes the pll can change the bandwidth or oper ational mode of the loop filter manually or automatically. in automatic bandwidth control mode (auto = 1), the lock detector automatically switches between acquisition and tracking modes. automatic bandwidth c ontrol mode also is us ed to determi ne when the vco clock, cgmvclk, is safe to us e as the source for the base clock, cgmout. see 8.6.2 pll bandwidt h control register . if pll interrupts are enabled, th e software can wait for a pll interrupt request and then check the lock bit. if interrup ts are disabled, software can poll the lock bit cont inuously (during pll startup, usually) or at periodic intervals. in either case, when the lo ck bit is set, the vco clock is safe to use as the source for the base clock. see 8.4.3 base clock selector circuit . if the vco is select ed as the source for the base clock and the lock bit is clear, the pll has suffered a seve re noise hit and the software must take appropriate ac tion, depending on the application. see 8.7 interrupts for information and precaut ions on using interrupts. advance information mc68hc908mr24 ? rev. 4.1 116 clock generator module (cgm) freescale semiconductor clock generator module (cgm) these conditions apply when the pll is in automatic bandwidth control mode: the acq bit (see 8.6.2 pll bandwidth control register ) is a read-only indicator of the mode of the filter. for more information, see 8.4.2.2 acquisition and tracking modes . the acq bit is set when the vco fr equency is within a certain tolerance, ? trk , and is cleared when the vco frequency is out of a certain tolerance, ? unt . for more information, see 8.9 acquisition/lock ti me specifications . the lock bit is a read-only indica tor of the locked state of the pll. the lock bit is set when the vco frequency is within a certain tolerance, ? lock , and is cleared when the vco frequency is out of a certain tolerance, ? unl . for more information, see 8.9 acquisition/lock ti me specifications . cpu interrupts can occur if enabl ed (pllie = 1) when the pll?s lock condition changes, toggling the lock bit. for more information, see 8.6.1 pll control register . the pll also may operate in ma nual mode (auto = 0). manual mode is used by systems that do not requi re an indicator of the lock condition for proper operation. such systems typicall y operate well below f busmax and require fast startup. these c onditions apply when in manual mode: acq is a writable control bit that controls t he mode of the filter. before turning on the pll in manual mode, the acq bit must be clear. before entering tracking mode (acq = 1), software must wait a given time, t acq (see 8.9 acquisition/lock time specifications ), after turning on the pll by setting pllon in the pll control regi ster (pctl). software must wait a given time, t al , after entering tracking mode before selecting the pll as th e clock source to cgmout (bcs = 1). the lock bit is disabled. cpu interrupts from the cgm are disabled. clock generator module (cgm) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor clock generator module (cgm) 117 8.4.2.4 progr amming the pll use this 9-step procedur e to program the pll. table 8-1 lists the variables used and their meaning. 1. choose the desired bus frequency, f busdes . example: f busdes = 8 mhz 2. calculate the desir ed vco frequency, f vclkdes . f vclkdes = 4 x f busdes example: f vclkdes = 4 x 8 mhz = 32 mhz 3. using a referernce frequency, f rclk , equal to the crystal frequency, calculate the vco fre quency multiplier, n. round the result to the nearest integer. 4. calculate the vco frequency, f vclk . table 8-1. variable definitions variable definition f busdes desired bus clock frequency f vclkdes desired vco clock frequency f rclk chosen refereence crystal frequency f vclk calculated vco clock frequency f bus calculated bus clock frequency f nom nominal vco center frequency f vrs shifted fco center frequency f vclkdes f rclk n = example: n = 32 mhz 4 mhz = 8 mhz f vclk = n x f rclk example: f vclk = 8 x 4 mhz = 32 mhz advance information mc68hc908mr24 ? rev. 4.1 118 clock generator module (cgm) freescale semiconductor clock generator module (cgm) 5. calculate the bus frequency, f bus , and compare f bus with f busdes . 6. if the calculated f bus is not within the to lerance limits of your application, sele ct another f busdes or another f rclk . 7. using the value 4.9152 mhz for f nom , calculate the vco linear range multiplier, l. the linear range multiplier controls the frequency range of the pll. 8. calculate the vco cent er-of-range frequency, f vrs . the center- or-range frequency is the midpoint betw een the minimum and maximum frequencies attainable by the pll. f vrs = l x f nom example: f vrs = 7 x 4.9152 mhz = 34.4 mhz note: for proper operation, exceeding the recommended ma ximum bus frequency or vco frequency can cr ash the mcu. 9. program the pll r egisters accordingly: a. in the upper four bits of the pll programming r egister (ppg), program the binary equivalent of n. b. in the lower four bits of t he pll programming r egister (ppg), program the binary equivalent of l. f bus = f vclk 4 example: n = 32 mhz 4 mhz = 8 mhz l = round f vclk f nom example: l = 32 mhz 4.9152 mhz = 7 mhz ( ) f vrs ? f vclk | f nom 2 clock generator module (cgm) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor clock generator module (cgm) 119 8.4.2.5 special pr ogramming exceptions the programming method described in 8.4.2.4 programming the pll does not account for possible exceptions . a value of zero for n or l is meaningless when used in the equations given. to account for these exceptions: a zero value for n is interprete d exactly the same as a value of one. a zero value for l di sables the pll and prev ents its selection as the source for the base clock. (see 8.4.3 base clock selector circuit .) 8.4.3 base clock se lector circuit this circuit is used to select either the crystal clock, cgmxclk, or the vco clock, cgmvclk, as the source of the ba se clock, cgmout. the two input clocks go thro ugh a transition control ci rcuit that waits up to three cgmxclk cycles and three cg mvclk cycles to change from one clock source to the other. duri ng this time, cgmout is held in stasis. the output of the transition co ntrol circuit is then divided by two to correct the duty cycle. therefore, the bus clo ck frequency, which is one-half of the base clock frequency, is one-fourth the frequency of the selected clock (cgmxclk or cgmvclk). the bcs bit in the pll cont rol register (pctl) sele cts which clock drives cgmout. the vco clock c annot be selected as t he base clock source if the pll is not turned on. the pll cannot be turned off if the vco clock is selected. the pll cannot be tur ned on or off simultaneously with the selection or deselection of the vco clock. the vco clock also cannot be selected as the base clock source if the factor l is programmed to a 0. this value would set up a condition inco nsistent with the operation of the pll, so that the pll would be dis abled and the crystal clock would be forced as the source of the base clock. advance information mc68hc908mr24 ? rev. 4.1 120 clock generator module (cgm) freescale semiconductor clock generator module (cgm) 8.4.4 cgm exte rnal connections in its typical confi guration, the cgm requ ires seven external components. five of thes e are for the crystal o scillator and two are for the pll. the crystal oscillator is normally connected in a pierce oscillator configuration, as shown in figure 8-3 . figure 8-3 shows only the logical representation of the internal components and ma y not represent actual circuitry. the oscillator configurati on uses five components: 1. crystal, x 1 2. fixed capacitor, c 1 3. tuning capacitor, c 2 (can also be a fixed capacitor) 4. feedback resistor, r b 5. series resistor, r s (optional) the series resistor (r s ) is included in the diagram to follow strict pierce oscillator guidelines and may not be r equired for all rang es of operation, especially with high-frequency cr ystals. refer to the crystal manufacturer?s data for more information. figure 8-3 also shows the exter nal components for the pll: bypass capacitor, c byp filter capacitor, c f note: routing should be done with great care to mini mize signal cross talk and noise. (see 8.9 acquisition/lock time specifications for routing information and more info rmation on the filter capacitor?s value and its effects on pll performance.) clock generator module (cgm) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor clock generator module (cgm) 121 figure 8-3. cgm external connections 8.5 i/o signals this section describes the cg m input/output (i/o) signals. 8.5.1 crystal amplifi er input pin (osc1) the osc1 pin is an input to the crystal oscillator amplifier. 8.5.2 crystal amplifi er output pin (osc2) the osc2 pin is the output of the crystal oscillator inverting amplifier. c 1 c 2 c f simoscen cgmxclk r b x 1 r s * c byp osc1 osc2 v ss cgmxfc v dda *r s can be 0 (shorted) when used with higher-frequency crystals. v dd refer to manufacturer?s data. advance information mc68hc908mr24 ? rev. 4.1 122 clock generator module (cgm) freescale semiconductor clock generator module (cgm) 8.5.3 external filter capacitor pin (cgmxfc) the cgmxfc pin is required by the loop filter to fi lter out phase corrections. a small external capac itor is connected to this pin. note: to prevent noise problems, c f should be placed as close to the cgmxfc pin as possible, with minimum routing distances and no routing of other si gnals across the c f connection. 8.5.4 pll analog power pin (v dda ) v dda is a power pin used by the analog portions of the pll. connect the v dda pin to the same volt age potential as the v dd pin. note: route v dda carefully for maximum noise immunity and place bypass capacitors as close as possible to the package. 8.5.5 oscillator e nable signal (simoscen) the simoscen signal come s from the system int egration module (sim) and enables the osci llator and pll. 8.5.6 crystal output frequency signal (cgmxclk) cgmxclk is the crystal o scillator output signal. it runs at the full speed of the crystal (f xclk ) and comes directly from the crystal oscillator circuit. figure 8-3 shows only the logical relati on of cgmxclk to osc1 and osc2 and may not represent the actual circuitry. the duty cycle of cgmxclk is unknown and may depend on the crystal and other external factors. also, the frequen cy and amplitude of cgmxclk can be unstable at startup. 8.5.7 cgm base cl ock output (cgmout) cgmout is the clock output of the cgm. this signal goes to the sim, which generates the mcu clocks. cg mout is a 50 percent duty cycle clock running at twice the bus frequency. cgmout is software clock generator module (cgm) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor clock generator module (cgm) 123 programmable to be eith er the oscillator outpu t, cgmxclk, divided by two or the vco clock, cgmvclk, divided by two. 8.5.8 cgm cpu interrupt (cgmint) cgmint is the interrupt signal generated by the pll lock detector. 8.6 cgm registers these registers control and m onitor operation of the cgm: pll control r egister (pctl) see 8.6.1 pll control register . pll bandwidth contro l register (pbwc) see 8.6.2 pll bandwidth control register . pll programming register (ppg) see 8.6.3 pll programming register . figure 8-4 is a summary of the cgm registers. addr. register name bit 7654321bit 0 $005c pll control register (pctl) see page 124. read: pllie pllf pllon bcs 1111 write: r r r r r reset:00101111 $005d pll bandwidth control register (pbwc) see page 126. read: auto lock acq xld 0000 write: r r r r r reset:00000000 $005e pll programming register (ppg) see page 128. read: mul7 mul6 mul5 mul4 vrs7 vrs6 vrs5 vrs4 write: reset:01100110 r= reserved notes: 1. when auto = 0, pllie is forced to logic 0 and is read-only. 2. when auto = 0, pllf and lock read as logic 0. 3. when auto = 1, acq is read-only. 4. when pllon = 0 or vrs[7: 4] = $0, bcs is forced to logic 0 and is read-only. 5. when pllon = 1, the pll programming register is read-only. 6. when bcs = 1, pllon is forced set and is read-only. figure 8-4. cgm i/o register summary advance information mc68hc908mr24 ? rev. 4.1 124 clock generator module (cgm) freescale semiconductor clock generator module (cgm) 8.6.1 pll control register the pll control register (pctl) contains the in terrupt enable and flag bits, the on/off switch, and th e base clock selector bit. pllie ? pll interrupt enable bit this read/write bi t enables the pll to gener ate an interrupt request when the lock bit toggles, sett ing the pll flag, pllf. when the auto bit in the pll bandwidth c ontrol register (pbwc) is clear, pllie cannot be written and reads as logic 0. reset clears the pllie bit. 1 = pll interrupts enabled 0 = pll interrupts disabled pllf ? pll interrupt flag this read-only bit is set wheneve r the lock bit toggles. pllf generates an interrupt request if th e pllie bit also is set. pllf always reads as logic 0 when t he auto bit in the pll bandwidth control register (pbwc) is clear . clear the pllf bi t by reading the pll control register. re set clears the pllf bit. 1 = change in lock condition 0 = no change in lock condition note: do not inadvertently cl ear the pllf bit. any re ad or read-modify-write operation on the pll control regi ster clears the pllf bit. address: $005c bit 7654321bit 0 read: pllie pllf pllon bcs 1111 write: r rrrr reset:00101111 r= reserved figure 8-5. pll cont rol register (pctl) clock generator module (cgm) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor clock generator module (cgm) 125 pllon ? pll on bit this read/write bit activates t he pll and enables the vco clock, cgmvclk. pllon cannot be cleared if the vco clock is driving the base clock, cgmout (bcs = 1). see 8.4.3 base clock selector circuit . reset sets this bit so that the loop can stabi lize as the mcu is powering up. 1 = pll on 0 = pll off bcs ? base clock select bit this read/write bit sele cts either the crystal oscillator output, cgmxclk, or the vco clock, cgm vclk, as the sour ce of the cgm output, cgmout. cgmout frequency is one-ha lf the frequency of the selected clock. bcs cannot be set while t he pllon bit is clear. after toggling b cs, it may take up to three cgmxclk and three cgmvclk cycles to complete the tr ansition from one source clock to the other. during the transition, cgmout is held in stasis. see 8.4.3 base clock sel ector circuit . reset clears the bcs bit. 1 = cgmvclk divided by two drives cgmout 0 = cgmxclk divided by two drives cgmout note: pllon and bcs have built-in protec tion that prevents the base clock selector circuit from se lecting the vco clock as the source of the base clock if the pll is of f. therefore, pllon cannot be cleared when bcs is set, and bcs cannot be set when pllon is clear. if the pll is off (pllon = 0), selecting cgmvclk require s two writes to the pll control register. see 8.4.3 base clock se lector circuit . pctl[3:0] ? unimplemented bits these bits provide no function and always read as logic 1s. advance information mc68hc908mr24 ? rev. 4.1 126 clock generator module (cgm) freescale semiconductor clock generator module (cgm) 8.6.2 pll bandwidth control register the pll bandwidth contro l register (pbwc): selects automatic or manual (software-controlled) bandwidth control mode indicates when the pll is locked in automatic bandwidth control mode , indicates when the pll is in acquisition or tracking mode in manual operation, forces the pll into acquisition or tracking mode auto ? automatic bandwidth control bit this read/write bit sele cts automatic or manual bandwidth control. when initializing the p ll for manual operation (auto = 0), clear the acq bit before turning on the pll. reset cl ears the auto bit. 1 = automatic bandwidth control 0 = manual bandwidth control lock ? lock indicator bit when the auto bit is set, lock is a read-only bit that becomes set when the vco clock, cgmvclk, is lo cked (running at the programmed frequency). when the auto bit is clear, lock reads as logic 0 and has no meaning. reset clears the lock bit. 1 = vco frequency correct or locked 0 = vco frequency inco rrect or unlocked address: $005d bit 7654321bit 0 read: auto lock acq xld 0000 write: r rrrr reset:00000000 r= reserved figure 8-6. pll bandwidth control register (pbwc) clock generator module (cgm) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor clock generator module (cgm) 127 acq ? acquisition mode bit when the auto bit is set, acq is a read-only bit that indicates whether the pll is in acquisition mode or tr acking mode. when the auto bit is clear, acq is a read/write bit that controls whether the pll is in acquisiti on or tracking mode. in automatic bandwidth control mode (auto = 1), the last-written value from manual operati on is stored in a te mporary location and is recovered when manual oper ation resumes. rese t clears this bit, enabling acquisition mode. 1 = tracking mode 0 = acquisition mode xld ? crystal loss detect bit when the vco output, cgmvclk, is driving cgmout, this read/write bit can in dicate whether the crystal reference frequency is active or not. to check th e status of the crystal reference, follow these steps: 1. write a logic 1 to xld. 2. wait n 4 cycles. (n is the vco frequency multiplier.) 3. read xld. 1 = crystal referenc e is not active. 0 = crystal reference is active. the crystal loss detect function wor ks only when the bcs bit is set, selecting cgmvclk to drive cg mout. when bcs is clear, xld always reads as logic 0. pbwc[3:0] ? reserved for test these bits enable test functions not available in user mode. to ensure software portability fr om development systems to user applications, software should write 0s to pb wc[3:0] whenever writing to pbwc. advance information mc68hc908mr24 ? rev. 4.1 128 clock generator module (cgm) freescale semiconductor clock generator module (cgm) 8.6.3 pll programming register the pll programming register (ppg ) contains the programming information for the modulo feedb ack divider and the programming information for the hardware configuratio n of the vco. mul[7:4] ? multip lier select bits these read/write bits control the m odulo feedback divider that selects the vco frequency multiplier, n. see 8.4.2.1 pll circuits and 8.4.2.4 programming the pll . a value of $0 in the multiplier select bits configures the m odulo feedback divider th e same as a value of $1. reset initializes these bits to $6 to give a defaul t multiply value of 6. note: the multiplier select bits have built-in protection that prevents them from being written when the p ll is on (pllon = 1). address: $005e bit 7654321bit 0 read: mul7 mul6 mul5 mul4 vrs7 vrs6 vrs5 vrs4 write: reset:01100110 figure 8-7. pll progra mming register (ppg) table 8-2. vco frequency mu ltiplier (n) selection mul7:mul6:mul5:mul4 vco frequency multiplier (n) 0000 1 0001 1 0010 2 0011 3 1101 13 1110 14 1111 15 clock generator module (cgm) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor clock generator module (cgm) 129 vrs[7:4] ? vco r ange select bits these read/write bits control the hardware center-of-range linear multiplier l, which controls the hardware cent er-of-range frequency f vrs . see 8.4.2.1 pll circuits , 8.4.2.4 programming the pll and 8.6.1 pll control register . vrs[7:4] cannot be written when the pllon bit in the pll control register (pctl) is set. see 8.4.2.5 special programming exceptions . a value of $0 in the vco range select bits disables the pll and clears the bcs bit in the pctl. see 8.4.3 base clock selector circuit and 8.4.2.5 special programming exceptions for more information. reset initializes the bits to $6 to give a default range multiply value of 6. note: the vco range select bits have built-i n protection that prevents them from being written when the pll is on (p llon = 1) and prevents selection of the vco clo ck as the source of the base clock (bcs = 1) if the vco range select bits are all clear. the vco range select bits must be programmed correctly. incorrect programming may result in failur e of the pll to achieve lock. 8.7 interrupts when the auto bit is set in the pll bandwidth control register (pbwc), the pll can generate a cpu interrupt request ev ery time the lock bit changes state. the pllie bit in the pll control register (pctl) enables cpu interrupts from the pll. pllf, the interrupt flag in the pctl, becomes set whether interrupts ar e enabled or not. when the auto bit is clear, cpu interrupts from the p ll are disabled and pllf reads as logic 0. software should read the lock bit after a pll interrupt request to see if the request was due to an entry into lock or an exit fr om lock. when the pll enters lock, the vco clock, cgmvclk, divided by two can be selected as the cgmout source by setting bcs in the pctl. when the pll exits lock, the vco clock fr equency is corrupt, and appropriate precautions should be taken. if the application is not frequency- sensitive, interrupts s hould be disabled to prevent pll interrupt service advance information mc68hc908mr24 ? rev. 4.1 130 clock generator module (cgm) freescale semiconductor clock generator module (cgm) routines from impedi ng software performance or from exceeding stack limitations. note: software can select the cgmvclk divided by two as the cgmout source even if the p ll is not locked (lock = 0). therefore, software should make sure the pll is lo cked before setting the bcs bit. 8.8 wait mode the wait instruction pu ts the mcu in low pow er-consumption standby mode. the wait instruction does not affect the cgm. before entering wait mode, software can disengage and turn off the pll by clearing the bcs and pllon bits in the pll control r egister (pctl). less power-sensitive applications can disengage the pll without turning it off. applications that require the pll to wake the mcu from wait mode also can deselect the pll output without turning off the pll. 8.9 acquisition/lock time specifications the acquisition and lo ck times of the pll are, in many applications, the most critical pll desi gn parameters. proper desig n and use of the pll ensures the highest stability and lowest acquisi tion/lock times. 8.9.1 acquisition/lock time definitions typical control systems refer to the ac quisition time or lock time as the reaction time, within specified tolera nces, of the system to a step input. in a pll, the step input occurs when the pll is turned on or when it suffers a noise hit. the tolerance is usually specified as a percent of the step input or when the ou tput settles to the desi red value plus or minus a percent of the frequen cy change. therefore, t he reaction time is constant in this definit ion, regardless of the si ze of the step input. for example, consider a system with a 5 percent acqui sition time tolerance. if a command instruct s the system to change from 0 hz to 1 mhz, the acquisition time is the time ta ken for the frequency to reach clock generator module (cgm) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor clock generator module (cgm) 131 1mhz 50 khz. fifty khz = 5% of the 1-mh z step input. if the system is operating at 1 mhz and suff ers a ?100-khz noise hit, the acquisition time is the time taken to re turn from 900 khz to 1 mhz 5 khz. five khz = 5% of the 100-khz step input. other systems refer to ac quisition and lock times as the time the system takes to reduce the error between the actual output and the desired output to within specified toleranc es. therefore, the acquisition or lock time varies according to the original error in the output . minor errors may not even be registered. typical pll applications prefer to use this definition because the system requires the out put frequency to be within a certain tolerance of the desired fr equency regardless of the size of the initial error. the discrepancy in these definitions ma kes it difficult to specify an acquisition or lock time for a typical pll. therefor e, the definitions for acquisition and lock times for this module are: acquisition time, t acq , is the time the pll ta kes to reduce the error between the actual output fr equency and the desired output frequency to less than the tra cking mode entry tolerance, ? trk . acquisition time is based on an initial frequency error, (f des ? f orig )/f des , of not more than 100 percent. in automatic bandwidth control mode (see 8.4.2.3 manual and automatic pll bandwidth modes ), acquisition time expires when the acq bit becomes set in the pll bandwid th control regi ster (pbwc). lock time, t lock , is the time the pll ta kes to reduce the error between the actual output fr equency and the desired output frequency to less than the lo ck mode entry tolerance, ? lock . lock time is based on an init ial frequency error, (f des ? f orig )/f des , of not more than 100 percent. in automat ic bandwidth control mode, lock time expires when t he lock bit becomes set in the pll bandwidth control r egister (pbwc). see 8.4.2.3 manual and automatic pll bandwidth modes . obviously, the acquisition and lock ti mes can vary according to how large the frequency error is and may be shorter or longer in many cases. advance information mc68hc908mr24 ? rev. 4.1 132 clock generator module (cgm) freescale semiconductor clock generator module (cgm) 8.9.2 parametric in fluences on reaction time acquisition and lock times are designed to be as short as possible while still providing the highest possible stability. these reaction times are not constant, however. many factors di rectly and indirect ly affect the acquisition time. the most critical parameter which af fects the reaction times of the pll is the reference frequency, f rdv . this frequency is the input to the phase detector and controls how often the pll makes corr ections. for stability, the corrections must be small compared to t he desired frequency, so several corrections are requir ed to reduce the frequency error. therefore, the slower the reference the longer it takes to make these corrections. this parameter is also un der user control via the choice of crystal frequency, f xclk . another critical parameter is the external filter capacitor. the pll modifies the voltage on the vco by adding or subtracting charge from this capacitor. therefore, the rate at which t he voltage changes for a given frequency error (thus change in charge) is propo rtional to the capacitor size. the si ze of the capa citor also is related to the stability of the pll. if the capacitor is too small, the pl l cannot make small enough adjustments to the volt age and the system cannot lo ck. if the capacitor is too large, the pl l may not be able to ad just the voltage in a reasonable time. see 8.9.3 choosing a fi lter capacitor . also important is th e operating voltage po tential applied to v dda . the power supply potential alters the charac teristics of the p ll. a fixed value is best. variable supplies, such as bat teries, are acceptable if they vary within a known range at very slow speeds. noise on the power supply is not acceptable, because it caus es small frequency errors which continually change the acquisi tion time of the pll. temperature and processing also can af fect acquisition time because the electrical characteristics of the pll change. the part operates as specified as long as these influences stay within the specified limits. external factors, however, can caus e drastic changes in the operation of the pll. these factors include noise injected into t he pll through the filter capacitor filter, capacitor leakage, stray impedanc es on the circuit board, and even hum idity or circuit board contamination. clock generator module (cgm) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor clock generator module (cgm) 133 8.9.3 choosing a filter capacitor as described in 8.9.2 parametric in fluences on re action time , the external filter capacitor, c f , is critical to the stability and reaction time of the pll. the pll is also dependent on reference frequency and supply voltage. the value of t he capacitor must, ther efore, be chosen with supply potential and reference fre quency in mind. for proper operation, the external filter capac itor must be chosen a ccording to this equation: for acceptable values of c fact , see 8.9 acquisition/lock time specifications . for the value of v dda , choose the voltage potential at which the mcu is operating. if the power supply is variable, choose a value near the middle of the r ange of possible supply values. this equation does not always yield a commonl y available capacitor size, so round to t he nearest available size. if the value is between two different sizes, choose the higher va lue for better stability. choosing the lower size may seem attractive for acquisition time impr ovement, but the pll can become unstable. also, alwa ys choose a capacitor with a tight tolerance ( 20 percent or better ) and low dissipation. 8.9.4 reaction ti me calculation the actual acquisition and lock time s can be calculated using the equations here. these e quations yield nominal values under these conditions: correct selection of filter capacitor, c f see 8.9.3 choosing a filter capacitor . room temperature operation negligible external leakage on cgmxfc negligible noise the k factor in the equatio ns is derived from in ternal pll parameters. k acq is the k factor when the pll is configured in acquisition mode, and c f c fact v dda f rdv -------------- - ?? ?? ?? = advance information mc68hc908mr24 ? rev. 4.1 134 clock generator module (cgm) freescale semiconductor clock generator module (cgm) k trk is the k factor when the pll is configured in tracking mode. see 8.4.2.2 acquisiti on and tracking modes . note the inverse proportionality bet ween the lock time and the reference frequency. in automatic bandwidth control m ode, the acquisition and lock times are quantized into units based on th e reference frequency. see 8.4.2.3 manual and automatic pll bandwidth modes . a certain number of clock cycles, n acq , is required to ascertain th at the pll is within the tracking mode entry tolerance, ? trk , before exiting acquisition mode. a certain number of clock cycles, n trk , is required to a scertain that the pll is within the lock mode entry tolerance, ? lock . therefore, the acquisition time, t acq , is an integer multiple of n acq /f rdv , and the acquisition to lock time, t al , is an integer multiple of n trk /f rdv . also, since the average frequency over t he entire measurem ent period must be within the specified tole rance, the total time usually is longer than t lock as calculated in th e previous example. in manual mode, it is us ually necessary to wait considerably longer than t lock before selecting the pll clock (see 8.4.3 base clock selector circuit ) because the factors described in 8.9.2 parametric influences on reaction time may slow the lock time considerably. t acq v dda f rdv -------------- - ?? ?? ?? 8 k acq --------------- ?? ?? = t al v dda f rdv -------------- - ?? ?? ?? 4 k trk -------------- ?? ?? = t lock t acq t al + = mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor pulse-width modulator for motor control (pwmmc) 135 advance information ? mc68hc908mr24 section 9. pulse-width modulator for motor control (pwmmc) 9.1 contents 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 9.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 9.4 timebase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 9.4.1 resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 9.4.2 prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 9.5 pwm generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 9.5.1 load operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143 9.5.2 pwm data overflow and underf low conditions. . . . . . . . . 148 9.6 output control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 9.6.1 selecting six independent pwms or three complementary pwm pairs . . . . . . . . . . . . . . 148 9.6.2 dead-time insertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 9.6.3 top/bottom correction with motor phase current polarity sensing . . . . . . . . . . . . . . . . . . . . . . . . 154 9.6.4 output polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 9.6.5 pwm output port contro l. . . . . . . . . . . . . . . . . . . . . . . . . . 160 9.7 fault protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 9.7.1 fault condition input pi ns . . . . . . . . . . . . . . . . . . . . . . . . . 166 9.7.1.1 fault pin filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 9.7.1.2 automatic mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 9.7.1.3 manual mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 9.7.2 software output disable . . . . . . . . . . . . . . . . . . . . . . . . . . 170 9.7.3 output port control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170 9.8 initialization and the pwm en bit . . . . . . . . . . . . . . . . . . . . . . 171 9.9 pwm operation in wait mode . . . . . . . . . . . . . . . . . . . . . . . . 172 advance information mc68hc908mr24 ? rev. 4.1 136 pulse-width modulator for motor control (pwmmc) freescale semiconductor pulse-width modulator for motor control 9.10 control logic block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 9.10.1 pwm counter registers. . . . . . . . . . . . . . . . . . . . . . . . . . .173 9.10.2 pwm counter modulo registers . . . . . . . . . . . . . . . . . . . . 174 9.10.3 pwm x value registers. . . . . . . . . . . . . . . . . . . . . . . . . . .175 9.10.4 pwm control register 1. . . . . . . . . . . . . . . . . . . . . . . . . . .176 9.10.5 pwm control register 2. . . . . . . . . . . . . . . . . . . . . . . . . . .178 9.10.6 dead-time write-once register . . . . . . . . . . . . . . . . . . . . 181 9.10.7 pwm disable mapping write-once register . . . . . . . . . . . 181 9.10.8 fault control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 9.10.9 fault status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 9.10.10 fault acknowledge regist er. . . . . . . . . . . . . . . . . . . . . . . . 186 9.10.11 pwm output control r egister . . . . . . . . . . . . . . . . . . . . . . 187 9.11 pwm glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 9.2 introduction this section describes the pulse-width modulator for motor control (pwmmc, version a). the mc 68hc908mr24 pwm module can generate three complementary pw m pairs or six independent pwm signals. these pwm si gnals can be center-aligned or edge-aligned. a block diagram of the pw m module is shown in figure 9-1 . a12-bit timer pwm counter is co mmon to all six channels. pwm resolution is one clock period fo r edge-aligned operation and two clock periods for center-aligned operation. the clock peri od is dependent on the internal oper ating frequency (f op ) and a programmable prescaler. the highest resolution for edge- aligned operation is 125 ns (f op = 8 mhz). the highest resolution for center-aligned operation is 250 ns (f op = 8 mhz). when generating complementary pwm signals, the m odule features automatic dead-time insertion to t he pwm output pairs and transparent toggling of pwm data bas ed upon sensed motor phase current polarity. a summary of the pwm r egisters is shown in figure 9-2 . pulse-width modulator for motor control (pwmmc) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor pulse-width modulator for motor control (pwmmc) 137 9.3 features features of the pwmmc include: three complimentary pwm pairs or six independent pwm signals edge-aligned pwm signals or center-a ligned pwm signals pwm signal polarity control 20-ma current sink capability on pwm pins manual pwm output cont rol through software programmable fault protection complementary mode featuring: ? dead-time insertion ? separate top/bottom pulse width correction via current sensing or programmable software bits figure 9-1. pwm module block diagram pwm1pin pwm2pin pwm channels 3 and 4 pwm3pin pwm4pin pwm channels 5 and 6 pwm5pin pwm6pin timebase cpu bus output control coil current polarity pins 3 4 fault interrupt pins 12 control logic block 8 pwm channels 1 and 2 fault protection advance information mc68hc908mr24 ? rev. 4.1 138 pulse-width modulator for motor control (pwmmc) freescale semiconductor pulse-width modulator for motor control addr. register name bit 7 6 5 4 3 2 1 bit 0 $0020 pwm control register 1 (pctl1) see page 176. read: disx disy pwmint pwmf isens1 isens0 ldok pwmen write: reset: 0 0 0 0 0 0 0 0 $0021 pwm control register 2 (pctl2) see page 179. read: ldfq1 ldfq0 0 ipol1 ipol2 ipol3 prsc1 prsc0 write: reset: 0 0 0 0 0 0 0 0 $0022 fault control register (fcr) see page 182. read: fint4 fmode4 fint3 fmode3 fint2 fmode2 fint1 fmode1 write: reset: 0 0 0 0 0 0 0 0 $0023 fault status register (fsr) see page 184. read: fpin4 fflag4 fpin3 fflag3 fpin2 fflag2 fpin1 fflag1 write: reset: u 0 u 0 u 0 u 0 $0024 fault acknowledge register (ftack) see page 186. read: 0 0 dt6 dt5 dt4 dt3 dt2 dt1 write: ftack4 ftack3 ftack2 ftack1 reset: 0 0 0 0 0 0 0 0 $0025 pwm output control register (pwmout) see page 187. read: 0 outctl out6 out5 out4 out3 out2 out1 write: reset: 0 0 0 0 0 0 0 0 $0026 pwm counter register high (pcnth) see page 173. read: 0 0 0 0 bit 11 bit 10 bit 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 $0027 pwm counter register low (pcntl) see page 173. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $0028 pwm counter modulo register high (pmodh) see page 174. read: 0 0 0 0 bit 11 bit 10 bit 9 bit 8 write: reset: 0 0 0 0 x x x x r= reserved bold = buffered x = indeterminate figure 9-2. register su mmary (sheet 1 of 3) pulse-width modulator for motor control (pwmmc) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor pulse-width modulator for motor control (pwmmc) 139 $0029 pwm counter modulo register low (pmodl) see page 174. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: xx x x x x xx $002a pwm 1 value register high (pval1h) see page 175. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 $002b pwm 1 value register low (pval1l) see page 175. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $002c pwm 2 value register high (pval2h) see page 175. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 $002d pwm 2 value register low (pval2l) see page 175. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $002e pwm 3 value register high (pval3h) see page 175. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 $002f pwm 3 value register low (pval3l) see page 175. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $0030 pwm 4 value register high (pval4h) see page 175. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 $0031 pwm 4 value register low (pval4l) see page 175. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 addr. register name bit 7 6 5 4 3 2 1 bit 0 r= reserved bold = buffered x = indeterminate figure 9-2. register su mmary (sheet 2 of 3) advance information mc68hc908mr24 ? rev. 4.1 140 pulse-width modulator for motor control (pwmmc) freescale semiconductor pulse-width modulator for motor control $0032 pwm 5 value register high (pval5h) see page 175. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 $0033 pwm 5 value register low (pval5l) see page 175. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $0034 pwm 6 value register high (pval6h) see page 175. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 $0035 pwm 6 value register low (pmval6l) see page 175. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $0036 dead-time write-once register (deadtm) see page 181. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 1 1 1 1 1 1 1 1 $0037 pwm disable mapping write-once register (dismap) see page 181. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 1 1 1 1 1 1 1 1 addr. register name bit 7 6 5 4 3 2 1 bit 0 r= reserved bold = buffered x = indeterminate figure 9-2. register su mmary (sheet 3 of 3) pulse-width modulator for motor control (pwmmc) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor pulse-width modulator for motor control (pwmmc) 141 9.4 timebase this section provides a di scussion of the timebase. 9.4.1 resolution in center-aligned mode, a 12-bit up/down counter is used to create the pwm period. therefore, the pwm resolution in center-aligned mode is two clocks (highest reso lution is 250 ns @ f op = 8 mhz) as shown in figure 9-3 . the up/down counter uses the value in the timer modulus register to det ermine its maximum count. the pwm period will equal: [(timer modulus) x (pwm clock period) x 2]. figure 9-3. center-aligned pwm (positive polarity) up/down counter modulus = 4 pwm = 0 pwm = 1 pwm = 2 pwm = 3 pwm = 4 period = 8 x (pwm clock period) advance information mc68hc908mr24 ? rev. 4.1 142 pulse-width modulator for motor control (pwmmc) freescale semiconductor pulse-width modulator for motor control for edge-aligned m ode, a 12-bit up-only counter is used to create the pwm period. therefore, the pwm re solution in edge- aligned mode is one clock (highest resolution is125 ns @ f op = 8 mhz) as shown in figure 9-4 . again, the timer modulus regi ster is used to determine the maximum count. the pw m period will equal: [(timer modulus) x (pwm clock period)]. center-aligned operation versus edge-aligned operation is determined by the option edge. see 5.3 functional description . figure 9-4. edge-aligned pwm (positive polarity) up-only counter modulus = 4 pwm = 0 pwm = 1 pwm = 2 pwm = 3 pwm = 4 period = 4 x (pwm clock period) pulse-width modulator for motor control (pwmmc) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor pulse-width modulator for motor control (pwmmc) 143 9.4.2 prescaler to permit lower pwm freque ncies, a prescaler is provided which will divide the pwm clock frequen cy by 1, 2, 4, or 8. table 9-1 shows how setting the prescaler bits in pwm control register 2 affects the pwm clock frequency. this prescaler is bu ffered and will not be used by the pwm generator until the ldok bit is set and a new pwm reload cycle begins. 9.5 pwm generators pulse-width modulator (pwm) gen erators are discussed in this subsection. 9.5.1 load operation to help avoid erroneous pulse widths and pwm periods, the modulus, prescaler, and pwm value register s are buffered. new pwm values, counter modulus values, and prescalers can be loaded from their buffers into the pwm module every one, two, four, or eight pwm cycles. ldfq1 and ldfq0 in pwm control register 2 are used to control this reload frequency, as shown in table 9-2 . when a reload cycle arrives, regardless of whether an actual reload occurs (as determined by the ldok bit), the pwm reload flag bit in pwm control register 1 will be set. if the pwmint bit in pwm control r egister 1 is set, a cpu interrupt request will be gene rated when pwmf is set. software can use this table 9-1. pwm prescaler prescaler bits prsc1 and prsc0 pwm clock frequency 00 f op 01 f op /2 10 f op /4 11 f op /8 advance information mc68hc908mr24 ? rev. 4.1 144 pulse-width modulator for motor control (pwmmc) freescale semiconductor pulse-width modulator for motor control interrupt to calculate new pwm param eters in real ti me for the pwm module. for ease of software, the ldfqx bits are buffered. when the ldfqx bits are changed, the rel oad frequency will not c hange until the previous reload cycle is co mpleted. see figure 9-5 . note: when reading the ldfqx bits, the value is the buffered value (for example, not necessarily the value being acted upon). figure 9-5. rel oad frequency change pwmint enables cpu interrupt requests as shown in figure 9-6 . when this bit is set, cpu interrupt r equests are generated when the pwmf bit is set. when the pwmint bit is clear, pwm interrup t requests are inhibited. pwm reloads will still occu r at the reload rate , but no interrupt requests will be generated. table 9-2. pwm reload frequency reload frequency bits ldfq1 and ldfq0 pwm reload frequency 00 every pwm cycle 01 every 2 pwm cycles 10 every 4 pwm cycles 11 every 8 pwm cycles reload reload reload reload reload reload reload change reload frequency to every 4 cycles change reload frequency to every cycle pulse-width modulator for motor control (pwmmc) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor pulse-width modulator for motor control (pwmmc) 145 figure 9-6. pwm interrupt requests to prevent a partial rel oad of pwm parameters fr om occurring while the software is still calculating them, an interlock bit contro lled from software is provided. this bit informs t he pwm module that all the pwm parameters have been calc ulated, and it is ?okay? to use them. a new modulus, prescaler, and/or pwm va lue cannot be loaded into the pwm module until the ldok bi t in pwm control regist er 1 is set. when the ldok bit is set, these new values are loaded into a second set of registers and used by t he pwm generator at the beginning of the next pwm reload cycle as shown in figure 9-7 , figure 9-8 , figure 9-9 , and figure 9-10 . after these values are l oaded, the ldok bit is cleared. note: when the pwm module is en abled (via the pwmen bit), a load will occur if the ldok bit is set. even if it is not set, an in terrupt will occur if the pwmint bit is set. to prevent this, the soft ware should clear the pwmint bit before enab ling the pwm module. latch v dd cpu interrupt reset d ck pwmint pwmf pwm reload read pwmf as 1, write pwmf as 0 or reset request advance information mc68hc908mr24 ? rev. 4.1 146 pulse-width modulator for motor control (pwmmc) freescale semiconductor pulse-width modulator for motor control figure 9-7. center-ali gned pwm value loading figure 9-8. center-a ligned loading of modulus ldok = 1 modulus = 3 pwm value = 1 ldok = 1 modulus = 3 pwm value = 2 up/down counter pwm ldfq1:ldfq0 = 00 (reload every cycle) ldok = 0 modulus = 3 pwm value = 2 ldok = 0 modulus = 3 pwm value = 1 pwmf set pwmf set pwmf set pwmf set ldok = 1 pwm value = 1 modulus = 2 ldok = 1 pwm value = 1 modulus = 3 ldok = 1 pwmvalue = 1 modulus = 2 ldok = 1 pwm value = 1 modulus = 1 ldok = 0 pwm value = 1 modulus = 2 up/down counter pwm ldfq1:ldfq0 = 00 (reload every cycle) pwmf set pwmf set pwmf set pwmf set pwmf set pulse-width modulator for motor control (pwmmc) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor pulse-width modulator for motor control (pwmmc) 147 figure 9-9. edge-al igned pwm value loading figure 9-10. edge-al igned modulus loading ldok = 1 modulus = 3 pwm value = 1. ldok = 1 modulus = 3 pwm value = 2 up-only counter pwm ldfq1:ldfq0 = 00 (reload every cycle) ldok = 0 modulus = 3 pwm value = 2. ldok = 0 modulus = 3 pwm value = 1 ldok = 0 modulus = 3 pwm value = 1 pwmf set pwmf set pwmf set pwmf set pwmf set ldok = 1 modulus = 3 pwm value = 2 ldok = 1 modulus = 4 pwm value = 2 ldok = 1 modulus = 2 pwm value = 2 up-only counter pwm ldfq1:ldfq0 = 00 (reload every cycle) ldok = 0 modulus = 1 pwm value= 2 pwmf set pwmf set pwmf set pwmf set advance information mc68hc908mr24 ? rev. 4.1 148 pulse-width modulator for motor control (pwmmc) freescale semiconductor pulse-width modulator for motor control 9.5.2 pwm data overflow and underflow conditions the pwm value regist ers are 16-bit registers. although the counter is only 12 bits, the user ma y write a 16-bit signed value to a pwm value register. as shown in figure 9-3 and figure 9-4 , if the pwm value is less than or equal to ze ro, the pwm will be inacti ve for the ent ire period. conversely, if the pwm value is greater than or equal to the timer modulus, the pwm will be active fo r the entire period. refer to table 9-3 . note: the terms ?active? and ?inactive? refer to the asserted and negated states of the pwm signals and sh ould not be confused with the high- impedance state of the pwm pins. 9.6 output control this subsection discu sses output control. 9.6.1 selecting six i ndependent pwms or three co mplementary pwm pairs the pwm outputs can be configured as six independent pwm channels or three complementary channel pairs. the option indep determines which mode is used (see 5.3 functional description ). if complementary operation is chosen, the pwm pins are paired as shown in figure 9-11 . operation of one pair is then determined by one pwm value register. this type of operation is meant for use in motor drive circuits such as the one in figure 9-12 . table 9-3. pwm data overfl ow and underflow conditions pwmvalxh:pwmvalxl cond ition pwm value used $0000?$0fff normal per register contents $1000?$7fff overflow $fff $8000?$ffff underflow $000 pulse-width modulator for motor control (pwmmc) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor pulse-width modulator for motor control (pwmmc) 149 figure 9-11. complementary pairing figure 9-12. typi cal ac motor drive pwm value register pwms 1 and 2 pwms 3 and 4 pwms 5 and 6 output control pwm value register pwm value register pwm1 pin pwm2 pin pwm3 pin pwm4 pin pwm5 pin pwm6 pin polarity & dead-time insertion pwm 1 pwm 2 pwm 3 pwm 4 pwm 5 pwm 6 ac to motor inputs advance information mc68hc908mr24 ? rev. 4.1 150 pulse-width modulator for motor control (pwmmc) freescale semiconductor pulse-width modulator for motor control when complementary operation is us ed, two additiona l features are provided: dead-time insertion separate top/bottom pulse widt h correction to correct for distortions caused by the mo tor drive characteristics if independent operation is chosen, each pwm has it s own pwm value register. 9.6.2 dead-time insertion as shown in figure 9-12 , in complementary mo de, each pwm pair can be used to drive top-side/b ottom-side transistors. when controlling dc-to-ac inverters such as this, the top and bottom pwms in one pair should never be active at th e same time. in figure 9-12 , if pwm1 and pwm2 were on at the same time, large currents would flow thro ugh the two transistors as they discharge the bus capacitor. the igbts coul d be weakened or destroyed. simply forcing the two pwms to be in versions of each other is not always sufficient. since a time delay is associated with tu rning off the transistors in the motor drive, there must be a dead-time between the deactivation of one pwm and the ac tivation of the other. a dead-time can be specified in the dead-time write-once register. this 8-bit value specifies the number of cpu clock cycles to use for the dead- time. the dead-time is not affected by changes in the pwm period caused by the prescaler. dead-time insertion is achieved by feeding the top pw m outputs of the pwm generator into dead-time generators, as shown in figure 9-13 . current sensing determines which pw m value of a pwm generator pair to use for the t op pwm in the next pwm cycle. see 9.6.3 top/bottom correction with motor pha se current pola rity sensing . when output control is enabled, the odd out bits , rather than the pwm generator outputs, are fed into the dead-time generators. see 9.6.5 pwm output port control . mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor pulse-width modulator for motor control (pwmmc) 151 pulse-width modulator for motor control (pwmmc) figure 9-13. dead-time generators fault polarity/output drive pwmgen<1:6> pwmpair12 pwmpair34 pwmpair56 mux pwm(top) outx select predt(top) dead time top/bottom generation postdt (top) top/bottom generation top/bottom generation top bottom top bottom top bottom pwm1 pwm2 pwm3 pwm4 pwm5 pwm6 6 mux pwm (top) outx select predt (top) mux pwm (top) outx select predt (top) mux pwm (top) outx select predt (top) dead-time dead time postdt (top) dead-time dead time postdt (top) dead-time (top) (top) (top) (pwm1) (pwm2) (pwm3) (pwm4) (pwm5) (pwm6) output control out1 out3 out5 outctl out2 out4 out6 (outctl) current sensing pwm generator advance information mc68hc908mr24 ? rev. 4.1 152 pulse-width modulator for motor control (pwmmc) freescale semiconductor pulse-width modulator for motor control whenever an input to a dead-time generator transitions, a dead-time is inserted (for example, both pwms in the pair are forced to their inactive state). the bottom pwm signal is generated from the top pwm and the dead-time. in the case of output control enabled , the odd outx bits control the top pwms, the even outx bits control the bottom pwms with respect to t he odd outx bits (see table 9-6 ). figure 9-14 shows the effects of the dead -time insertion. as seen in figure 9-14 , some pulse width dist ortion occurs when the dead-time is inserted. the active pulse widths are reduced. for example, in figure 9-14 , when the pwm value regi ster is equal to two, the ideal waveform (with no dead-time) has pul se widths equal to four. however, the actual pulse widths shrink to two after a dead-time of two was inserted. in this example, with the prescaler set to divide by one and center-aligned operation selected, th is distortion can be compensated for by adding or s ubtracting half the dead-time value to or from the pwm register value. this correcti on is further described in 9.6.3 top/bottom correction with motor phase current polarity sensing . further examples of dead-tim e insertion are shown in figure 9-15 and figure 9-16 . figure 9-15 shows the effects of de ad-time insertion at the duty cycle boundaries (near 0 perce nt and 100 percent duty cycles). figure 9-16 shows the effects of dead-ti me insertion on pulse widths smaller than the dead time. pulse-width modulator for motor control (pwmmc) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor pulse-width modulator for motor control (pwmmc) 153 figure 9-14. effects of dead-time insertion figure 9-15. dead- time at duty cycle boundaries pwm value = 2 pwm value = 2 pwm value = 3 pwm1 w/ pwm2 w/ pwm1 w/ pwm2 w/ no dead time no dead time dead time = 2 dead time = 2 2 2 2 2 up/down counter modulus = 4 2 2 up/down counter modulus = 3 pwm value = 1 pwm value = 3 pwm value = 3 pwm1 w/ no dead time pwm2 w/ no dead time pwm1 w/ dead time = 2 pwm2 w/ dead time = 2 2 2 2 2 pwm value = 1 advance information mc68hc908mr24 ? rev. 4.1 154 pulse-width modulator for motor control (pwmmc) freescale semiconductor pulse-width modulator for motor control figure 9-16. dead time and small pulse widths 9.6.3 top/bottom correction with mo tor phase current polarity sensing ideally, when complementary pairs are used, the pwm pairs are inversions of each other, as shown in figure 9-17 . when pwm1 is active, pwm2 is inactive, and vice versa. in this case, the motor terminal voltage is never allowed to float and is strictly controlled by the pwm waveforms. however, when dead time is inserted, the motor voltage is allowed to float momentarily during the dead-time interval, creating a distortion in the motor current wavefo rm. this distortion is aggr avated by dissimilar turn-on and turn-off delays of each of the transistors. for a typical motor drive inverter as shown in figure 9-12 , for a given top/bottom transistor pair, only one of the transistors will be effective in controlling the output voltage at any giv en time depending on the direction of the motor current fo r that pair. to achieve distortion correction, one of two di fferent correction factor s must be added to the desired pwm value, dependi ng on whether the top or bottom transistor is controlling the output voltage. therefore, the so ftware is responsible for calculating both co mpensated pwm values and placing them in an odd/even pwm register pair. by supplying the pwm module with information regarding which transistor (top or bottom) is controlling the 3 3 3 3 3 3 up/down counter moudulus = 3 pwm value = 2 pwm value = 3 pwm value = 2 pwm value = 1 pwm1 w/ no dead time pwm2 w/ no dead time pwm1 w/ dead time = 3 pwm2 w/ dead time = 3 pulse-width modulator for motor control (pwmmc) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor pulse-width modulator for motor control (pwmmc) 155 output voltage at any given time (for in stance, the current polarity for that motor phase), the pwm module se lects either the odd or even numbered pwm value regi ster to be used by the pwm generator. current sensing or programmable so ftware bits are then used to determine which pwm value to use. if the current sensed at the motor for that pwm pair is positive (voltage on current pin isx is low) or bit ipolx in pwm control register 2 is low, the top pwm value is used for the pwm pair. likewise, if the current sensed at the motor for that pwm pair is negative (voltage on current pin isx is high ) or bit ipolx in pwm control register 2 is high, the bottom pwm value is used. see table 9-4 . figure 9-17. ideal complement ary operation (dead time = 0) up/down counter modulus = 4 pwm value = 1 pwm1 pwm2 pwm value = 2 pwm3 pwm4 pwm value = 3 pwm5 pwm6 advance information mc68hc908mr24 ? rev. 4.1 156 pulse-width modulator for motor control (pwmmc) freescale semiconductor pulse-width modulator for motor control note: this text assumes the user will prov ide current sense circuitry which causes the voltage at the correspo nding input pin to be low for positive current and high for negative current. see figure 9-18 for current convention. in addition, it assumes the top pwms are pwms 1, 3, and 5 while the bottom pwms are pwms 2, 4, and 6. figure 9-18. current convention table 9-4. current sense pins current sense pin or bit voltage on current sense pin or ipolx bit pwm value register used pwms affected is1 or ipol1 logic 0 pwm value register 1 pwms 1 and 2 is1 or ipol1 logic 1 pwm value register 2 pwms 1 and 2 is2 or ipol2 logic 0 pwm value register 3 pwms 3 and 4 is2 or ipol2 logic 1 pwm value register 4 pwms 3 and 4 is3 or ipol3 logic 0 pwm value register 5 pwms 5 and 6 is3 or ipol3 logic 1 pwm value register 6 pwms 5 and 6 i+ i- pulse-width modulator for motor control (pwmmc) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor pulse-width modulator for motor control (pwmmc) 157 to allow for correction based on differ ent current sensing methods or correction controlled by software, the isens1 and isens0 bits in pwm control register 1 are provided to choose the correcti on method. these bits provide correc tion according to table 9-5 . if correction is to be done in softwa re or is not necessary, setting isens1:isens0 = 00 or = 01 causes the correction to be based on bits ipol1, ipol2, and ipol3 in pwm control register 2. if correction is not required, the user can initialize the ipolx bits a nd then only load one pwm value regist er per pwm pair. to allow the user to use a curr ent sense scheme based upon sensed phase voltage during dead time, sett ing isens1:isens0 = 10 causes the polarity of the ix pin to be latched when both the top and bottom pwms are off (for exam ple, during the dead time). at the 0 percent and 100 percent duty cycle boundar ies, there is no d ead time so no new current value is sensed. to accommodate other current sensing schemes, setting isens1:isens0 = 11 causes the polarity of the current sense pin to be latched half-way into the pwm cycle in center-aligne d mode and at the end of the cycle in edge-aligned mode. therefore, even at 0 percent and 100 percent duty cycle, t he current is sensed. table 9-5. correction methods current correction bits isens1 and isens0 correction method 00 01 bits ipol1, ipol2, and ipol3 used for correction 10 current sensing on pins is1 , is2 , and is3 occurs during the dead time. 11 current sensing on pins is1 , is2 , and is3 occurs at the half cycle in center-aligned mode and at the end of the cycle in edge-aligned mode. advance information mc68hc908mr24 ? rev. 4.1 158 pulse-width modulator for motor control (pwmmc) freescale semiconductor pulse-width modulator for motor control distortion correction is only availabl e in complementary mode. at the beginning of the pwm peri od, the pwm uses this latched current value or polarity bit to dec ide whether the top pw m value or bottom pwm value is used. figure 9-19 shows an example of to p/bottom correction for pwms 1 and 2. note: the ipolx bits and the values latched on the isx pins are buffered so that only one pwm regist er is used per pwm cycle. if the ipolx bits or the current sense values change du ring a pwm period, this new value will not be used until the next pwm period . the isensx bits are not buffered; therefore, c hanging the current sensi ng method could affect the present pwm cycle. figure 9-19. top/bottom corr ection for pwms 1 and 2 when the pwm is first enabled by sett ing pwmen, pwm value registers 1, 3, and 5 will be used if the isensx bits are configured for current sensing correction. this is because no current will have previously been sensed. pwm1 pwm2 pwm value reg. 1 = 1 pwm value reg. 2 = 2 is1 positive is1 positive is1 negative is1 negative pwm = 1 pwm = 1 pwm = 2 pwm = 2 pulse-width modulator for motor control (pwmmc) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor pulse-width modulator for motor control (pwmmc) 159 9.6.4 output polarity the output polarity of the pwms is determined by two options: topneg and botneg. the top polarit y option, topneg, con trols the polarity of pwms 1, 3, and 5. the bottom polari ty option, botneg , controls the polarity of pwms 2, 4, and 6. positi ve polarity means that when the pwm is active, the pwm output is high . conversely, negative polarity means that when the pwm is acti ve, pwm output is low. see figure 9-20 . note: both bits are found in the config register, which is a write-once register. this reduces the chances of the software inadvertently changing the polarity of the pwm si gnals and possibly damaging the motor drive hardware. figure 9-20. pwm polarity up/down counter modulus = 4 pwm <= 0 pwm = 1 pwm = 2 pwm = 3 pwm >= 4 up-only counter modulus = 4 pwm <= 0 pwm = 1 pwm = 2 pwm = 3 pwm >= 4 center-aligned positive polarity ed ge-aligned positive polarity advance information mc68hc908mr24 ? rev. 4.1 160 pulse-width modulator for motor control (pwmmc) freescale semiconductor pulse-width modulator for motor control figure 9-19. pwm polarity (continued) 9.6.5 pwm output port control conditions may arise in which the pwm pins need to be individually controlled. this is made possible by the pwm output co ntrol register (pwmout) shown in figure 9-21 . up/down counter modulus = 4 pwm <= 0 pwm = 1 pwm = 2 pwm = 3 pwm >= 4 up-only counter modulus = 4 pwm <= 0 pwm = 1 pwm = 2 pwm = 3 pwm >= 4 center-aligned negative polarity edge-aligned negative polarity address: $0025 bit 7654321bit 0 read: 0 outctl out6 out5 out4 out3 out2 out1 write: reset:00000000 = unimplemented figure 9-21. pwm output c ontrol register (pwmout) pulse-width modulator for motor control (pwmmc) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor pulse-width modulator for motor control (pwmmc) 161 if the outctl bit is set, the pwm pins can be controlled by the outx bits. these bits behave according to table 9-6 . when outctl is set, the polarity options toppol and botpol will still affect the outputs. in addition, if complement ary operation is in use, the pwm pairs will not be allowed to be active simultaneously, and dead time will still not be violated. when outc tl is set and complimentary operation is in use, the odd outx bits are inputs to the dead-time generators as shown in figure 9-14 . dead time is inserted whenever the odd outx bit toggles as shown in figure 9-22 . although dead time is not inserted when the even outx bits change, there wi ll be no dead-time violation as shown in figure 9-23 . setting the outctl bit does not di sable the pwm gener ator and current sensing circuitry. they continue to r un, but are no longer controlling the output pins. in add ition, outctl will control the pwm pins even when pwmen = 0. when outctl is cleared, the outputs of the pwm generator become the inputs to the dead-time and outp ut circuitry at the beginning of the next pwm cycle. note: to avoid an unexpected dead-time occurr ence, it is recommended that the outx bits be cleared prior to entering and prior to exiting individual pwm output control mode. table 9-6. outx bits outx bit complementary mode independent mode out1 1 ? pwm1 is active. 0 ? pwm1 is inactive. 1 ? pwm1 is active. 0 ? pwm1 is inactive. out2 1 ? pwm2 is complement of pwm 1. 0 ? pwm2 is inactive. 1 ? pwm2 is active. 0 ? pwm2 is inactive. out3 1 ? pwm3 is active. 0 ? pwm3 is inactive. 1 ? pwm3 is active. 0 ? pwm3 is inactive. out4 1 ? pwm4 is complement of pwm 3. 0 ? pwm4 is inactive. 1 ? pwm4 is active. 0 ? pwm4 is inactive. out5 1 ? pwm5 is active. 0 ? pwm5 is inactive. 1 ? pwm5 is active. 0 ? pwm5 is inactive. out6 1 ? pwm 6 is complement of pwm 5. 0 ? pwm6 is inactive. 1 ? pwm6 is active. 0 ? pwm6 is inactive. advance information mc68hc908mr24 ? rev. 4.1 162 pulse-width modulator for motor control (pwmmc) freescale semiconductor pulse-width modulator for motor control figure 9-22. dead-time i nsertion during outctl = 1 figure 9-23. dead-time i nsertion during outctl = 1 up/down counter modulus =4 pwm1 pwm2 dead time = 2 outctl out1 out2 2 pwm1/pwm2 2 2 dead time inserted as part of normal pwm operation as controlled by current sensing and pwm generator dead time inserted due to setting of out1 bit dead time inserted due to clearing of out1 bit pwm value = 3 dead time up/down counter modulus = 4 dead time = 2 outctl pwm1 pwm2 out1 out2 2 pwm1/pwm2 2 2 pwm value = 3 dead time inserted because when outctl was set, the state of out1 was such that pwm1 was directed to toggle dead time inserted because out1 toggles, directing pwm1 to toggle no dead time inserted because out1 is not toggling dead time 2 pulse-width modulator for motor control (pwmmc) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor pulse-width modulator for motor control (pwmmc) 163 9.7 fault protection conditions may arise in the external drive circuitry which require that the pwm signals become inacti ve immediately, such as an overcurrent fault condition. furthermore, it may be desirable to selectively disable pwm(s) solely with software. one or more pwm pins c an be disabled (forced to their inactive state) by applying a logic high to any of the four external fault pins or by writing a logic high to either of the disabl e bits (disx and disy in pwm control register 1). figure 9-25 shows the structure of the pwm disabling scheme. while the pwm pi ns are disabled, they are forced to their inactive state. the pwm generator c ontinues to run ? only the output pins are disabled. to allow for different motor configur ations and the controlling of more than one motor, the pwm di sabling function is or ganized as two banks, bank x and bank y. bank information combines with information from the disable mapping register to al low selective pwm disabling. fault pin 1, fault pin 2, and pwm disable bit x constitute the di sabling function of bank x. fault pin 3, f ault pin 4, and pwm disabl e bit y constitute the disabling functi on of bank y. figure 9-24 and figure 9-26 show the disable mapping write-once regist er and the decodi ng scheme of the bank which selectively disables pwm( s). when all bits of the disable mapping register ar e set, any disabl e condition will di sable all pwms. a fault can also generat e a cpu interrupt. each fault pin has its own interrupt vector. address: $0037 bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:11111111 figure 9-24. pw m disable mapping write-once register (dismap) advance information mc68hc908mr24 ? rev. 4.1 164 pulse-width modulator for motor control (pwmmc) freescale semiconductor pulse-width modulator for motor control figure 9-25. pwm disabli ng scheme (sheet 1 of 2) fault pin2 fint2 cycle start logic high for fault bank x disable fmode2 disx clear by writing 1 to ftack2 interrupt request two shot sq r sq r sq r sample filter one fpin2 fflag2 manual mode auto mode software x disable fault pin 2 disable the example is of fault pin 2 with disx. fault pin 4 with disy is logically similar and affects bank y disable. note: in manual mode (fmode = 0), faults 2 and 4 may be cleared on ly if a logic level low at the input of the fault pin is prese nt. mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor pulse-width modulator for motor control (pwmmc) 165 pulse-width modulator for motor control (pwmmc) figure 9-25. pwm disabli ng scheme (sheet 2 of 2) fault pin1 fint1 cycle start logic high for fault bank x disable fmode1 clear by writing 1 to ftack1 interrupt request two shot sq r sq r sample filter one fflag1 manual mode auto mode fault pin 1 disable the example is of fault pin 1. fault pin 3 is logically similar and affects bank y disable. note: in manual mode (fmode = 0), faults 1 and 3 may be clear ed regardless of the logic level at the input of the fault pin. fpin1 advance information mc68hc908mr24 ? rev. 4.1 166 pulse-width modulator for motor control (pwmmc) freescale semiconductor pulse-width modulator for motor control figure 9-26. pwm disabling decode scheme 9.7.1 fault condition input pins a logic high level on a fault pin disables t he respective pwm(s) determined by the bank and the disabl e mapping register. each fault pin incorporates a filter to assist in rejecting spur ious faults. all of the external fault pins ar e software-configurable to re-enable the pwms either with the fault pin (automatic mode) or with software (manual mode). each fault pin has an associat ed fmode bit to control the pwm re-enabling method . automatic mode is select ed by setting the fmodex bit in the fault control register. manual mode is selected when fmodex is clear. bit 7 bit 3 bit 0 bit 1 bit 2 bit 4 bit 5 bit 6 bank x disable disable disable disable disable disable disable disable bank y pwm pin 1 pwm pin 2 pwm pin 3 pwm pin 4 pwm pin 5 pwm pin 6 pulse-width modulator for motor control (pwmmc) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor pulse-width modulator for motor control (pwmmc) 167 9.7.1.1 fault pin filter each fault pin incorporates a filter to assist in determining a genuine fault condition. after a fault pin has been l ogic low for one cpu cycle, a rising edge (logic high) w ill be synchronously samp led once per cpu cycle for two cycles. if both samp les are detected logic high, the corresponding fpin bit and fflag bit will be set. the fpin bit wil l remain set until the corresponding fault pin is logic lo w and synchronously sampled once in the following cpu cycle. 9.7.1.2 automatic mode in automatic mode, the pw m(s) are disabled imm ediately once a filtered fault condition is detec ted (logic high). the pwm(s ) remain disabled until the filtered fault condition is cl eared (logic low) and a new pwm cycle begins as shown in figure 9-27 . clearing the corresponding fflagx event bit will not enable t he pwms in automatic mode. figure 9-27. pwm disabling in automatic mode the filtered fault pin?s logic state is reflected in th e respective fpinx bit. any write to this bit is overwritten by the pin state. the fflagx event bit is set with each rising edg e of the respective faul t pin after filtering has been applied. to clear the ffla gx bit, the user mu st write a 1 to the corresponding ftackx bit. pwm(s) pwm(s) enabled pwm(s) disabled (inactive) filtered fault pin advance information mc68hc908mr24 ? rev. 4.1 168 pulse-width modulator for motor control (pwmmc) freescale semiconductor pulse-width modulator for motor control if the fintx bit is set, a fault c ondition resulting in setting the corresponding fflag bit will also latc h a cpu interrupt request. the interrupt request latch is not clear ed until one of t he following actions occurs: the fflagx bit is cleared by wr iting a 1 to th e corresponding ftackx bit. the fintx bit is cleared. thi s will not clear the fflagx bit. a reset automatically clears all four interrupt latches. if prior to a vector fetc h, the interrupt request la tch is cleared by one of the above actions, a cpu interrupt wi ll no longer be requested. a vector fetch does not alter the state of the pwms, the fflagx event flag, or fintx. note: if the fflagx or fintx bits are not cleared duri ng the interrupt service routine, the inte rrupt request latch will not be cleared. 9.7.1.3 manual mode in manual mode, t he pwm(s) are disabled im mediately once a filtered fault condition is detec ted (logic high). the pwm(s ) remain disabled until software clears the corresponding fflagx event bi t and a new pwm cycle begins. in manual m ode, the fault pins are grouped in pairs, each pair sharing common functionality. a fault condition on pi ns 1 and 3 may be cleared, allowing the pwm(s) to enable at the start of a pwm cycle regardless of the logic leve l at the fault pin. see figure 9-28 . a fault condition on pins 2 and 4 can only be cleared, allowing the pwm(s) to enable, if a logic low level at the fault pin is present at the start of a pwm cycle. see figure 9-29 . pulse-width modulator for motor control (pwmmc) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor pulse-width modulator for motor control (pwmmc) 169 figure 9-28. pwm disabling in manual mode (example 1) figure 9-29. pwm disabling in manual mode (example 2) the function of the fault control and event bits is the same as in automatic mode except that the pwms are not re-enabled until the fflagx event bit is cleared by writ ing to the ftackx bit and the filtered fault condition is cleared (logic low). pwm(s) enabled pwm(s) enabled pwm(s) disabled fflagx cleared filtered fault pin 1 or 3 pwm(s) enabled pwm(s) enabled pwm(s) disabled fflagx cleared filtered fault pin 2 or 4 advance information mc68hc908mr24 ? rev. 4.1 170 pulse-width modulator for motor control (pwmmc) freescale semiconductor pulse-width modulator for motor control 9.7.2 software output disable setting pwm disable bi t disx or disy in pw m control register 1 immediately disables the correspondi ng pwm pins as determined by the bank and disable mapping register. t he pwm pin(s) remain disabled until the pwm disable bit is clea red and a new pwm cycle begins as shown in figure 9-30 . setting a pwm disable bi t does not latch a cpu interrupt request, and ther e are no event flags as sociated with the pwm disable bits. 9.7.3 output port control when operating the pwms using the outx bits (outctl = 1), fault protection applies as described in this secti on. due to the absence of periodic pwm cycles, fault conditi ons are cleared u pon each cpu cycle and the pwm outputs ar e re-enabled, provided all fault clearing conditions are satisfied. figure 9-30. pwm software disable pwm(s) enabled pwm(s) enabled pwm(s) disabled disable bit pulse-width modulator for motor control (pwmmc) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor pulse-width modulator for motor control (pwmmc) 171 9.8 initialization and the pwmen bit for proper operation, all r egisters should be initia lized and the ldok bit should be set before enabling the pwm via the pwmen bit. when the pwmen bit is first set, a reload will occur immediately, setting the pwmf flag and generating an interrupt if pwmi nt is set. in addition, in complementary mode, pwm value regist ers 1, 3, and 5 will be used for the first pwm cycle if current sens ing is selected. note: if the ldok bit is not set when pwmen is set after a reset , the prescaler and pwm values will be zero, but the modulus will be unknown. if the ldok bit is not set after the pwmen bit has been cleared then set (wit hout a reset), the modulus value that was last loaded will be used. if the dead-time regist er (deadtm) is c hanged after pwmen or outctl is set, an improper dead-time insertion could occur. however, the dead time can never be shor ter than the specified value. because of the equals-comparator ar chitecture of this pwm, the modulus = 0 case is cons idered illegal. therefore, the modulus register is not reset, and a m odulus value of 0 will result in waveforms inconsistent with the other modulus waveforms. see 9.10.2 pwm counter modulo registers . when pwmen is set, the pwm pi ns change from high impedance to outputs. at this time, assuming no fault condition is present, the pwm pins will drive according to the pwm values, polarity, and dead time. see the timing diagram in figure 9-31 . figure 9-31. pw men and pwm pins cpu clock pwmen pwm pins drive according to pwm value, polarity, and dead time hi-z if outctl = 0 hi-z if outctl = 0 advance information mc68hc908mr24 ? rev. 4.1 172 pulse-width modulator for motor control (pwmmc) freescale semiconductor pulse-width modulator for motor control when the pwmen bit is cl eared, this will occur: pwm pins will be thre e-stated unless outctl = 1. pwm counter is cleared and will no t be clocked. internally, the pwm generator will force its outputs to 0 to avoid glitches when the pwmen is set again. when pwmen is cleared, these features remain active: all fault circuitry manual pwm pin control via the pwmout register dead-time insertion when pwm pins change via the pwmout register note: the pwmf flag and pendi ng cpu interrupts ar e not cleared when pwmen = 0. 9.9 pwm operation in wait mode when the microcontroller is put in low-power wait mo de via the wait instruction, all clocks to the pwm module will c ontinue to run. if an interrupt is issued from the pwm modu le (via a reload or a fault), the microcontroller will exit wait mode. clearing the pwmen bit before enteri ng wait mode wi ll reduce power consumption in wait mode because the counter, presca ler divider, and ldfq divider will no longer be cl ocked. in additi on, power will be reduced because the pwms will no longer toggle. pulse-width modulator for motor control (pwmmc) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor pulse-width modulator for motor control (pwmmc) 173 9.10 control logic block this subsection provid es a description of t he control logic block. 9.10.1 pwm counter registers the pwm counter regist ers (pcnth and pcntl) display the 12-bit up/down or up-only counte r. when the high by te of the count er is read, the lower byte is latched. pcntl will hold this la tched value until it is read. address: $0026 bit 7654321bit 0 read: 0000bit 11bit 10bit 9bit 8 write: reset:00000000 = unimplemented figure 9-32. pwm counter register high (pcnth) address: $0027 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 = unimplemented figure 9-33. pwm counte r register low (pcntl) advance information mc68hc908mr24 ? rev. 4.1 174 pulse-width modulator for motor control (pwmmc) freescale semiconductor pulse-width modulator for motor control 9.10.2 pwm counte r modulo registers the pwm counter modulus registers (pmodh and pmodl) hold a 12- bit unsigned number that determi nes the maximum count for the up/down or up-only counter. in ce nter-aligned mode, the pwm period will be twice the modulus (assumi ng no prescaler). in edge-aligned mode, the pwm period will equal the modulus. to avoid erroneous pwm periods, this value is buffer ed and will not be used by the pwm generator until the ldok bit has been set and the next pwm load cycle begins. note: when reading this register , the value read is the buffer (not necessarily the value the pwm generator is currently using). because of the equals-comparator ar chitecture of this pwm, the modulus = 0 case is cons idered illegal. therefore, the modulus register is not reset, and a m odulus value of 0 will result in waveforms inconsistent with the ot her modulus waveforms. if a modulus of 0 is loaded, the counter wil l continually count down from $fff. this operation will not be tested or guaranteed (the user should consider it illegal). however, the dead- time constraints and fault conditions will still be guaranteed. address: $0028 bit 7654321bit 0 read: 0000 bit 11 bit 10 bit 9 bit 8 write: reset:0000 xxxx = unimplemented x = indeterminate figure 9-34. pwm counter m odulo register high (pmodh) address: $0029 bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:xxxxxxxx x = indeterminate figure 9-35. pwm counter modu lo register low (pmodl) pulse-width modulator for motor control (pwmmc) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor pulse-width modulator for motor control (pwmmc) 175 9.10.3 pwm x value registers each of the six pwms has a 16-bit pwm value register. the 16-bit signed value stored in this register determi nes the duty cycle of the pwm. the duty cycle is defin ed as: (pwm val ue/modulus) x 100. writing a number less than or equal to 0 causes the pwm to be off for the entire pwm per iod. writing a number great er than or equal to the 12-bit modulus causes the pwm to be on for the entire pwm period. if the complementary mode is se lected, the pwm pairs share pwm value registers. to avoid erroneous pwm pulses, this value is buffered and will not be used by the pwm generator until the ldok bit has been set and the next pwm load cycle begins. note: when reading these regi sters, the value read is the buffer (not necessarily the value the pwm g enerator is currently using). bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 bold = buffered figure 9-36. pwmx value registers high (pvalxh) bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 bold = buffered figure 9-37. pwmx valu e registers low (pvalxl) advance information mc68hc908mr24 ? rev. 4.1 176 pulse-width modulator for motor control (pwmmc) freescale semiconductor pulse-width modulator for motor control 9.10.4 pwm control register 1 pwm control register 1 (pctl1) controls pwm enabling/disabling, the loading of new modulus, pre scaler, pwm values, and the pwm correction method. in addition, this re gister contains the software disable bits to force the pwm outputs to thei r inactive states (according to the disable mapping register). disx ? software disable bit for bank x this read/write bit allows the user to disable one or more pwm pins in bank x. the pins that are di sabled are determined by the disable mapping write-once register. 1 = disable pwm pi ns in bank x 0 = re-enable pwm pins at beginning of next pwm cycle disy ? software disable bit for bank y this read/write bit allows the user to disable one or more pwm pins in bank y. the pins that are di sabled are determined by the disable mapping write-once register. 1 = disable pwm pi ns in bank y 0 = re-enable pwm pins at beginning of next pwm cycle pwmint ? pwm interrupt enable bit this read/write bit allows the us er to enable and disable pwm cpu interrupts. if set, a cpu interrupt will be pending when the pwmf flag is set. 1 = enable pwm cpu interrupts 0 = disable pwm cpu interrupts note: when pwmint is cleared, pending cpu interrupts are inhibited. address: $0020 bit 7654321bit 0 read: disx disy pwmint pwmf isens1 isens0 ldok pwmen write: reset:00000000 figure 9-38. pwm contro l register 1 (pctl1) pulse-width modulator for motor control (pwmmc) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor pulse-width modulator for motor control (pwmmc) 177 pwmf ? pwm reload flag this read/write bit is set at the beginning of every reload cycle regardless of the state of the ldok bit. this bit is cleared by reading pwm control register 1 with the pwmf fl ag set, then writ ing a logic 0 to pwmf. if another reload occu rs before the clearing sequence is complete, then writing logic 0 to pwmf has no effect. 1 = new reload cycle began. 0 = new reload cycle has not begun. note: when pwmf is cleared, pending pwm cpu interrupts are cleared (not including fault interrupts). isens1 and isens0 ? curr ent sense correction bits these read/write bits select the top/bottom correction scheme as shown in table 9-7 . note: the isensx bits are not bu ffered. changing the current sensing method can affect the present pwm cycle. ldok? load ok bit this read/write bit loads the prescale r bits of the pm ctl2 register and the entire pmmo dh/l and pwmvalh/l regist ers into a set of buffers. the buffered prescaler diviso r, pwm counter modulus value, and pwm pulse with take effect at the next pwm load. set ldok by reading it when it is l ogic 0 and then writing a lo gic 1 to it. ldok is table 9-7. correction methods current correction bits isens1 and isens0 correction method 00 01 bits ipol1, ipol2, and ipol3 are used for correction. 10 current sensing on pins is1 , is2 , and is3 occurs during the dead time. 11 current sensing on pins is1 , is2 , and is3 occurs at the half cycle in center-aligned mode and at the end of the cycle in edge-aligned mode. 1. the polarity of the isx pin is latched when both the top and bottom pwms are off. at the 0% and 100% duty cycle boundaries, there is no dead time, so no new current value is sensed. 2. current is sensed even with 0% and 100% duty cycle. advance information mc68hc908mr24 ? rev. 4.1 178 pulse-width modulator for motor control (pwmmc) freescale semiconductor pulse-width modulator for motor control automatically cleared after the new values are loaded or can be manually cleared before a reaload by writing a 0 to it. reset clears ldok. 1 = load prescaler, modulus, and pwm values. 0 = do not load new modulus, prescaler, and pwm values. note: the user should initialize the pwm re gisters and set the ldok bit before enabling the pwm. a pwm cpu interrupt r equest can still be generat ed when ldok is 0. pwmen ? pwm module enable bit this read/write bi t enables and disables the pwm generator and the pwm pins. when pwmen is clear, the pwm generator is disabled and the pwm pins are in the high-impedance state (unless outctl = 1). when the pwmen bit is set, the pwm generator and pwm pins are activated. for more information, see 9.8 initialization and the pwmen bit . 1 = pwm generator and pwm pins enabled 0 = pwm generator and pwm pins disabled 9.10.5 pwm control register 2 pwm control register 2 (pctl2) controls the pwm load frequency, the pwm correction method, and the pwm counter prescaler. for ease of software and to avoid er roneous pwm periods, some of these register bits are buffered. the pwm generator will not us e the prescaler value until the ldok bit has been set, and a new pwm cycle is starting. the correction bits are used at the beginning of each pwm cycle (if the isensx bits are configur ed for software correc tion). the load frequency bits are not used until the current load cycle is complete. note: the user should initialize this register before enabling the pwm. pulse-width modulator for motor control (pwmmc) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor pulse-width modulator for motor control (pwmmc) 179 ldfq1 and ldfq0 ? pw m load frequency bits these buffered read/write bits se lect the pwm cp u load frequency according to table 9-8 . note: when reading these bits, the valu e read is the buffer value (not necessarily the value the pwm g enerator is currently using). the ldfqx bits take effect when t he current load cycle is complete regardless of the state of the load okay bit, ldok. note: reading the lpfqx bit r eads the buffered values and not necessarily the values currently in effect. ipol1 ? top/bottom correction bi t for pwm pair 1 (pwms 1 and 2) this buffered read/write bit selects which pwm value register is used if top/bottom correction is to be achieved without current sensing. 1 = use pwm val ue register 2 0 = use pwm val ue register 1 address: $0021 bit 7654321bit 0 read: ldfq1 ldfq0 0 ipol1 ipol2 ipol3 prsc1 prsc0 write: reset:00000000 = unimplemented bold = buffered figure 9-39. pwm contro l register 2 (pctl2) table 9-8. pwm reload frequency reload frequency bits ldfq1 and ldfq0 pwm reload frequency 00 every pwm cycle 01 every 2 pwm cycles 10 every 4 pwm cycles 11 every 8 pwm cycles advance information mc68hc908mr24 ? rev. 4.1 180 pulse-width modulator for motor control (pwmmc) freescale semiconductor pulse-width modulator for motor control note: when reading this bit, the value read is the buffer value (not necessarily the value the output control block is currently using). the ipolx bits take effect at th e beginning of the next load cycle, regardless of the state of the load okay bit, ldok. ipol2 ? top/bottom correction bi t for pwm pair 2 (pwms 3 and 4) this buffered read/write bit selects which pwm value register is used if top/bottom correction is to be achieved without current sensing. 1 = use pwm val ue register 4 0 = use pwm val ue register 3 note: when reading this bit, the value read is the buffer value (not necessarily the value the output control block is currently using). ipol3 ? top/bottom correction bi t for pwm pair 3 (pwms 5 and 6) this buffered read/write bit selects which pwm value register is used if top/bottom correction is to be achieved without current sensing. 1 = use pwm val ue register 6 0 = use pwm val ue register 5 note: when reading this bit, the value read is the buffer value (not necessarily the value the output control block is currently using). prsc1 and prsc0 ? pwm prescaler bits these buffered read/write bits allo w the pwm clock frequency to be modified as shown in table 9-9 . note: when reading these bits, the valu e read is the buffer value (not necessarily the value the pwm g enerator is currently using). table 9-9. pwm prescaler prescaler bits prsc1 and prsc0 pwm clock frequency 00 f op 01 f op /2 10 f op /4 11 f op /8 pulse-width modulator for motor control (pwmmc) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor pulse-width modulator for motor control (pwmmc) 181 9.10.6 dead-time write-once register the dead-time write-once r egister (deadtm) holds an 8-bit value which specifies the number of cpu clock cycles to use for the dead time when complementary pwm mode is selected. after this register is written for the first time, it cannot be re written unless a reset occurs. dead time is not affected by changes to the prescaler value. 9.10.7 pwm disable mappi ng write-once register the pwm disable mapping write-once r egister (dismap) holds an 8-bit value which determines which pwm pi ns will be disabled if an external fault or software dis able occurs. for a further description of disable mapping, see 9.7 fault protection . after this register is written for the first time, it cannot be rewr itten unless a reset occurs. address: $0036 bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:11111111 figure 9-40. dead-time writ e-once register (deadtm) address: $0037 bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:11111111 figure 9-41. pw m disable mapping write-once register (dismap) advance information mc68hc908mr24 ? rev. 4.1 182 pulse-width modulator for motor control (pwmmc) freescale semiconductor pulse-width modulator for motor control 9.10.8 fault control register the fault control register (fcr) controls the faul t-protection circuitry fint4 ? fault 4 interrupt enable bit this read/write bit allows the cpu interrupt caus ed by faults on fault pin 4 to be enabled. the fault protec tion circuitry is independent of this bit and will always be active. if a f ault is detected, the pwm pins will still be disabled according to the disable mapping register. 1 = fault pin 4 will c ause cpu interrupts. 0 = fault pin 4 will not cause cpu interrupts. fmode4 ? fault mode select ion for fault pin 4 bit (automatic versus manual mode) this read/write bit allo ws the user to select between automatic and manual mode faults. fo r further description s of each mode, see 9.7 fault protection . 1 = automatic mode 0 = manual mode fint3 ? fault 3 interrupt enable bit this read/write bit allows the cpu interrupt caus ed by faults on fault pin 3 to be enabled. the fault protec tion circuitry is independent of this bit and will always be active. if a f ault is detected, the pwm pins will still be disabled according to the disable mapping register. 1 = fault pin 3 will c ause cpu interrupts. 0 = fault pin 3 will not cause cpu interrupts. address: $0022 bit 7654321bit 0 read: fint4fmode4fint3fmode3fint2fmode2fint1fmode1 write: reset:00000000 figure 9-42. fault cont rol register (fcr) pulse-width modulator for motor control (pwmmc) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor pulse-width modulator for motor control (pwmmc) 183 fmode3 ? fault mode select ion for fault pin 3 bit (automatic versus manual mode) this read/write bit allo ws the user to select between automatic and manual mode faults. fo r further description s of each mode, see 9.7 fault protection . 1 = automatic mode 0 = manual mode fint2 ? fault 2 interrupt enable bit this read/write bit allows the cpu interrupt caus ed by faults on fault pin 2 to be enabled. the fault protec tion circuitry is independent of this bit and will always be active. if a f ault is detected, the pwm pins will still be disabled according to the disable mapping register. 1 = fault pin 2 will c ause cpu interrupts. 0 = fault pin 2 will not cause cpu interrupts. fmode2 ? fault mode select ion for fault pin 2 bit (automatic versus manual mode) this read/write bit allo ws the user to select between automatic and manual mode faults . for further description s of each mode, see 9.7 fault protection . 1 = automatic mode 0 = manual mode fint1 ? fault 1 interrupt enable bit this read/write bit allows the cpu interrupt caus ed by faults on fault pin 1 to be enabled. the fault protec tion circuitry is independent of this bit and will always be active. if a f ault is detected, the pwm pins will still be disabled according to the disable mapping register. 1 = fault pin 1 will c ause cpu interrupts. 0 = fault pin 1 will not cause cpu interrupts. advance information mc68hc908mr24 ? rev. 4.1 184 pulse-width modulator for motor control (pwmmc) freescale semiconductor pulse-width modulator for motor control fmode1 ? fault mode select ion for fault pin 1 bit (automatic versus manual mode) this read/write bit allo ws the user to select between automatic and manual mode faults . for further description s of each mode, see 9.7 fault protection . 1 = automatic mode 0 = manual mode 9.10.9 fault status register the fault status register (fsr) is a read-only regist er that indicates the current fault status. fpin4 ? state of fault pin 4 bit this read-only bit a llows the user to read t he current stat e of fault pin 4. 1 = fault pin 4 is at logic 1. 0 = fault pin 4 is at logic 0. fflag4 ? fault event flag 4 the fflag4 event bit is set within two cpu cycles after a rising edge on fault pin 4. to clear the fflag4 bit, the user must write a 1 to the ftack4 bit in the faul t acknowledge register. 1 = a fault has occu rred on fault pin 4. 0 = no new faul t on fault pin 4 address: $0023 bit 7654321bit 0 read: fpin4 fflag4 fpin3 fflag3 fpin2 fflag2 fpin1 fflag1 write: reset:u0u0u0u0 = unimplemented u = unaffected figure 9-43. fault st atus register (fsr) pulse-width modulator for motor control (pwmmc) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor pulse-width modulator for motor control (pwmmc) 185 fpin3 ? state of fault pin 3 bit this read-only bit a llows the user to read t he current stat e of fault pin 3. 1 = fault pin 3 is at logic 1. 0 = fault pin 3 is at logic 0. fflag3 ? fault event flag 3 the fflag3 event bit is set within two cpu cycles after a rising edge on fault pin 3. to clear the fflag3 bit, the user must write a 1 to the ftack3 bit in the faul t acknowledge register. 1 = a fault has occu rred on fault pin 3. 0 = no new faul t on fault pin 3. fpin2 ? state of fault pin 2 bit this read-only bit a llows the user to read t he current stat e of fault pin 2. 1 = fault pin 2 is at logic 1. 0 = fault pin 2 is at logic 0. fflag2 ? fault event flag 2 the fflag2 event bit is set within two cpu cycles after a rising edge on fault pin 2. to clear the fflag2 bit, the user must write a 1 to the ftack2 bit in the faul t acknowledge register. 1 = a fault has occu rred on fault pin 2. 0 = no new faul t on fault pin 2 fpin1 ? state of fault pin 1 bit this read-only bit a llows the user to read t he current stat e of fault pin 1. 1 = fault pin 1 is at logic 1. 0 = fault pin 1 is at logic 0. fflag1 ? fault event flag 1 the fflag1 event bit is set within two cpu cycles after a rising edge on fault pin 1. to clear the fflag1 bit, the user must write a 1 to the ftack1 bit in the faul t acknowledge register. 1 = a fault has occu rred on fault pin 1. 0 = no new faul t on fault pin 1. advance information mc68hc908mr24 ? rev. 4.1 186 pulse-width modulator for motor control (pwmmc) freescale semiconductor pulse-width modulator for motor control 9.10.10 fault ac knowledge register the fault acknowledge r egister (ftack) is us ed to acknowledge and clear the fflags. in addition , it is used to moni tor the current sensing bits to test proper operation. ftack4 ? fault acknowledge 4 bit the ftack4 bit is used to acknowl edge and clear fflag4. this bit will always read 0. writing a 1 to th is bit will clear fflag4. writing a 0 will have no effect. ftack3 ? fault acknowledge 3 bit the ftack3 bit is used to acknowl edge and clear fflag3. this bit will always read 0. writing a 1 to th is bit will clear fflag3. writing a 0 will have no effect. ftack2 ? fault acknowledge 2 bit the ftack2 bit is used to acknowl edge and clear fflag2. this bit will always read 0. writing a 1 to th is bit will clear fflag2. writing a 0 will have no effect. ftack1 ? fault acknowledge 1 bit the ftack1 bit is used to acknowl edge and clear fflag1. this bit will always read 0. writing a 1 to th is bit will clear fflag1. writing a 0 will have no effect. address: $0024 bit 7654321bit 0 read: 0 0 dt6 dt5 dt4 dt3 dt2 dt1 write: ftack4 ftack3 ftack2 ftack1 reset:00000000 = unimplemented figure 9-44. fault acknow ledge register (ftack) pulse-width modulator for motor control (pwmmc) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor pulse-width modulator for motor control (pwmmc) 187 dt6 ? dead time 6 bit current sensing pin is3 is monito red immediately before dead time ends due to the assertion of pwm6. dt5 ? dead time 5 bit current sensing pin is3 is monito red immediately before dead time ends due to the assertion of pwm5. dt4 ? dead time 4 bit current sensing pin is2 is monito red immediately before dead time ends due to the assertion of pwm4. dt3 ? dead time 3 bit current sensing pin is2 is monito red immediately before dead time ends due to the assertion of pwm3. dt2 ? dead time 2 bit current sensing pin is1 is monito red immediately before dead time ends due to the assertion of pwm2. dt1 ? dead time 1 bit current sensing pin is1 is monito red immediately before dead time ends due to the assertion of pwm1. 9.10.11 pwm output control register the pwm output control regi ster (pwmout) is us ed to manually control the pwm pins. address: $0025 bit 7654321bit 0 read: 0 outctl out6 out5 out4 out3 out2 out1 write: reset:00000000 = unimplemented figure 9-45. pwm output c ontrol register (pwmout) advance information mc68hc908mr24 ? rev. 4.1 188 pulse-width modulator for motor control (pwmmc) freescale semiconductor pulse-width modulator for motor control outctl? output c ontrol enable bit this read/write bit allows the user to manually control the pwm pins. when set, the pwm generator is no l onger the input to the dead-time and output circuitry. the outx bits determine the state of the pwm pins. setting the outc tl bit does not dis able the pwm generator. the generator continues to run, but is no longer the input to the pwm dead-time and output circuitry. w hen outctl is cleared, the outputs of the pwm generator im mediately become the inputs to the dead- time and output circuitry. 1 = pwm outputs co ntrolled manually 0 = pwm outputs determ ined by pwm generator out6?out1? pwm pin ou tput control bits these read/write bits control the pwm pins according to table 9-10 . table 9-10. outx bits outx bit complementary mode independent mode out1 1 ? pwm1 is active. 0 ? pwm1 is inactive. 1 ? pwm1 is active. 0 ? pwm1 is inactive. out2 1 ? pwm2 is complement of pwm 1. 0 ? pwm2 is inactive. 1 ? pwm2 is active. 0 ? pwm2 is inactive. out3 1 ? pwm3 is active. 0 ? pwm3 is inactive. 1 ? pwm3 is active. 0 ? pwm3 is inactive. out4 1 ? pwm4 is complement of pwm 3. 0 ? pwm4 is inactive. 1 ? pwm4 is active. 0 ? pwm4 is inactive. out5 1 ? pwm5 is active. 0 ? pwm5 is inactive. 1 ? pwm5 is active. 0 ? pwm5 is inactive. out6 1 ? pwm 6 is complement of pwm 5. 0 ? pwm6 is inactive. 1 ? pwm6 is active. 0 ? pwm6 is inactive. pulse-width modulator for motor control (pwmmc) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor pulse-width modulator for motor control (pwmmc) 189 9.11 pwm glossary cpu cycle ? one internal bus cycle (1/f op ) pwm clock cycle (or period) ? one tick of the pwm counter (1/f op with no prescaler). see figure 9-46 . pwm cycle (or period) center-aligned mode: the time it takes the pwm counter to count up and count down (modulus * 2/f op assuming no prescaler). see figure 9-46 . edge-aligned mode: th e time it takes the pwm counter to count up (modulus/f op ). see figure 9-46 . figure 9-46. pwm clock cycle and pwm cycle definitions pwm clock cycle pwm cycle (or period) pwm pwm cycle (or period) center-aligned mode edge-aligned mode clock cycle advance information mc68hc908mr24 ? rev. 4.1 190 pulse-width modulator for motor control (pwmmc) freescale semiconductor pulse-width modulator for motor control pwm load frequency ? frequency at which new pwm parameters get loaded into the pwm. see figure 9-47 . figure 9-47. pwm load c ycle/frequency definition reload new modulus, prescaler, & pwm values if ldok = 1 reload new modulus, prescaler, & pwm values if ldok = 1 pwm load cycle ldfq1:ldfq0 = 01 ? reload every two cycles (1/pwm load frequency) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor monitor rom (mon) 191 advance information ? mc68hc908mr24 section 10. monitor rom (mon) 10.1 contents 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 10.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 10.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192 10.4.1 entering monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 10.4.2 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 10.4.3 echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 10.4.4 break signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 10.4.5 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 10.4.6 baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 10.5 security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 10.2 introduction this section describes the moni tor read-only memory (rom). the monitor rom (mon) allows comple te testing of the mcu through a single-wire interface wit h a host computer. advance information mc68hc908mr24 ? rev. 4.1 192 monitor rom (mon) freescale semiconductor monitor rom (mon) 10.3 features features of the mo nitor rom include: normal user-mode pin functionality one pin dedicated to serial co mmunication between monitor rom and host computer standard mark/space non-return -to-zero (nrz) communication with host computer 4800 baud?28.8 kbaud communicati on with host computer execution of code in random -access memory (ram) or rom flash programming 10.4 functional description the monitor rom receives and exec utes commands from a host computer. figure 10-1 shows a sample circuit used to enter monitor mode and communicate with a host computer via a standard rs-232 interface. simple monitor commands can access any memory address. in monitor mode, the mcu can exec ute host-computer code in ram while all mcu pins retain normal operating mode functions. all communication between the host computer and the m cu is through t he pta0 pin. a level-shifting and multiplexing in terface is required between pta0 and the host computer. pta0 is used in a wired-or configuration and requires a pullup resistor. monitor rom (mon) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor monitor rom (mon) 193 figure 10-1. moni tor mode circuit + + + + 10 m ? x1 v dd v hi mc145407 mc74hc125 68hc908 rst irq cgmxfc osc1 osc2 v ssa v ss v dd pta0 v dd 10 k ? 0.1 f 0.02 f 10 k ? 6 5 2 4 3 1 db-25 2 3 7 20 18 17 19 16 15 v dd v dd v dd 20 pf 20 pf 10 f 10 f 10 f 10 f 1 2 4 7 14 3 0.1 f 4.9152 mhz 10 k ? ptc2 v dd 10 k ? b a notes: position a ? bus clock = cgmxclk 4 or cgmvclk 4 position b ? bus clock = cgmxclk 2 (see note.) 5 6 pwmgnd v ssad v refl v dda 0.1 f v dda v ddad 0.1 f v ddad v refh 0.1 f v refh ptc3 ptc4 v dd 10 k ? advance information mc68hc908mr24 ? rev. 4.1 194 monitor rom (mon) freescale semiconductor monitor rom (mon) 10.4.1 entering monitor mode table 10-1 shows the pin conditions for entering monitor mode. enter monitor mode by either: executing a software inte rrupt instruction (swi) or applying a logic 0 and t hen a logic 1 to the rst pin once out of reset, t he mcu waits for the host to send eight security bytes. after receiving the security bytes, the mcu sends a break signal (10 consecutive logic 0s) to the host co mputer, indicating that it is ready to receive a command. the break signal also provides a timing reference to allow the host to determine the nec essary baud rate. monitor mode uses alter nate vectors for reset and swi. the alternate vectors are in the $fe page in stead of the $ff page and allow code execution from the internal monito r firmware instead of user code. the computer operating properly (cop) m odule is disabled in monitor mode as long as v hi is applied to either the irq pin or the rst pin. (see section 7. system int egration module (sim) for more information on modes of operation.) note: holding the ptc2 pin low when ent ering monitor mode causes a bypass of a divide-by-two stage at the oscillator. the cgmout frequency is equal to the cgmxclk frequency, and the osc1 i nput directly generates internal bus clocks. in th is case, the osc1 signal must have a 50 percent duty cycle at maximum bus frequency. table 10-1. mode selection irq pin ptc3 pin ptc4 pin pta0 pin ptc2 pin mode cgmout bus frequency v hi 1011monitor or v hi 1010monitor cgmxclk cgmxclk 2 ----------------------------- cgmvclk 2 ----------------------------- cgmout 2 -------------------------- cgmout 2 -------------------------- monitor rom (mon) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor monitor rom (mon) 195 table 10-2 is a summary of the differ ences between user mode and monitor mode. 10.4.2 data format communication with the monitor rom is in standard non-return-to-zero (nrz) mark/space data format. (see figure 10-2 and figure 10-3 .) figure 10-2. moni tor data format figure 10-3. sample monitor waveforms the data transmit and receive rate can be anywhere fr om 4800 baud to 28.8 kbaud. transmit and receive baud rates must be identical. table 10-2. mode differences modes functions cop reset vector high reset vector low swi vector high swi vector low user enabled $fffe $ffff $fffc $fffd monitor disabled (1) 1. if the high voltage (v hi ) is removed from the irq pin or the rst pin, the sim asserts its cop enable output. the cop is t he copd bit in the configuration register. $fefe $feff $fefc $fefd bit 5 start bit bit 0 bit 1 next stop bit start bit bit 2 bit 3 bit 4 bit 6 bit 7 bit 5 start bit bit 0 bit 1 next stop bit start bit bit 2 bit 3 bit 4 bit 6 bit 7 start bit bit 0 bit 1 next stop bit start bit bit 2 $a5 break bit 3 bit 4 bit 5 bit 6 bit 7 advance information mc68hc908mr24 ? rev. 4.1 196 monitor rom (mon) freescale semiconductor monitor rom (mon) 10.4.3 echoing as shown in figure 10-4 , the monitor rom immediately echoes each received byte back to the pt a0 pin for error checking. figure 10-4. read transaction any result of a command appears after the ec ho of the last byte of the command. 10.4.4 break signal a start bit followed by nine low bits is a break signal. see figure 10-5 . when the monitor receives a break sign al, it drives the pta0 pin high for the duration of tw o bits before echoi ng the break signal. figure 10-5. break transaction 10.4.5 commands the monitor rom uses these commands: read, read memory write, write memory iread, indexed read iwrite, indexed write readsp, read stack pointer run, run user program addr. high read read addr. high addr. low addr. low data echo sent to monitor result 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 missing stop bit 2--stop-bit delay before zero echo monitor rom (mon) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor monitor rom (mon) 197 table 10-3. read (r ead memory) command description read byte from memory operand specifies 2-byte address in high byte:low byte order data returned returns contents of specified address opcode $4a command sequence addr. high read read addr. high addr. low addr. low data echo sent to monitor result table 10-4. write (write memory) command description write byte to memory operand specifies 2-byte address in high byte:low byte order; low byte followed by data byte data returned none opcode $49 command sequence addr. high write write addr. high addr. low addr. low data echo sent to monitor data advance information mc68hc908mr24 ? rev. 4.1 198 monitor rom (mon) freescale semiconductor monitor rom (mon) note: a sequence of iread or iwrite commands can sequentially access a block of memory over the full 64-kbyte memory map. table 10-5. iread (i ndexed read) command description read next 2 bytes in me mory from last address accessed operand specifies 2-byte address in high byte:low byte order data returned returns contents of next two addresses opcode $1a command sequence table 10-6. iwrite (indexed write) command description write to last address accessed + 1 operand specifies single data byte data returned none opcode $19 command sequence data iread iread data echo sent to monitor result data iwrite iwrite data echo sent to monitor monitor rom (mon) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor monitor rom (mon) 199 table 10-7. readsp (read stack pointer) command description reads stack pointer operand none data returned returns stack pointer in high byte:low byte order opcode $0c command sequence table 10-8. run (run u ser program) command description executes rti instruction operand none data returned none opcode $28 command sequence sp high readsp readsp sp low echo sent to monitor result run run echo sent to monitor advance information mc68hc908mr24 ? rev. 4.1 200 monitor rom (mon) freescale semiconductor monitor rom (mon) 10.4.6 baud rate with a 4.9152-mhz crystal and the ptc2 pin at logic 1 during reset, data is transferred between t he monitor and host at 480 0 baud. if the ptc2 pin is at logic 0 during rese t, the monitor baud rate is 9600. 10.5 security a security feature discourages unaut horized reading of flash locations while in monitor mode. the host can bypass the securi ty feature at monitor mode entry by sending eight security bytes that match the bytes at locations $fff6?$fffd. locati ons $fff6?$fffd contain user- defined data. note: do not leave locati ons $fff6?$fffd blank . for security reasons, program locations $fff6?$fffd even if they are not used for vectors. during monitor mode entry, the mcu waits after the power-on reset for the host to send th e eight security bytes on pi n pta0. if the received bytes match those at location s $fff6?$fffd, the hos t bypasses the security feature and can read al l flash locations and execute code from flash. security remains bypa ssed until a power-on reset occurs. if the reset was not a power-on reset, security remains bypassed and security code entry is not required. (see figure 10-6 .) upon power-on reset, if the receiv ed bytes of the se curity code do not match the data at loca tions $fff6?$fffd, the host fails to bypass the security feature. the mcu remain s in monitor mode, but reading a flash location returns an invalid val ue and trying to exec ute code from flash causes an illegal address reset. after receiving the eight security bytes from the host, the mc u transmits a br eak character, signifying that it is ready to receive a command. note: the mcu does not transmit a break character unti l after the host sends the eight security bytes. monitor rom (mon) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor monitor rom (mon) 201 figure 10-6. monitor mode entry timing to determine whether the security c ode entered is correct, check to see if bit 6 of ram address $ 40 is set. if it is, then the correct security code has been entered and fl ash can be accessed. if the security sequence fails, t he device can be reset (via power-pin reset only) and brought up in monito r mode to attemp t another entry. after failing the securi ty sequence, the flash mode can also be bulk erased by executing an erase routine that was downloaded into internal ram. the bulk erase operation clears the security code locations so that all eight security bytes become $00. byte 1 byte 1 echo byte 2 byte 2 echo byte 8 byte 8 echo command command echo pa0 pa7 rst v dd 4096 + 32 cgmxclk cycles 24 bus cycles 256 bus cycles (minimum) 1 4 1 1 2 1 break notes: 2 = data return delay, 2 bit times 4 = wait 1 bit time before sending next byte. 4 from host from mcu 1 = echo delay, 2 bit times advance information mc68hc908mr24 ? rev. 4.1 202 monitor rom (mon) freescale semiconductor monitor rom (mon) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor timer interface a (tima) 203 advance information ? mc68hc908mr24 section 11. timer interface a (tima) 11.1 contents 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 11.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 11.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208 11.4.1 tima counter prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . .208 11.4.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 11.4.3 output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 11.4.3.1 unbuffered output compare . . . . . . . . . . . . . . . . . . . . . 210 11.4.3.2 buffered output com pare . . . . . . . . . . . . . . . . . . . . . . .211 11.4.4 pulse-width modulatio n (pwm) . . . . . . . . . . . . . . . . . . . . . 212 11.4.4.1 unbuffered pwm sig nal generation . . . . . . . . . . . . . . . 213 11.4.4.2 buffered pwm signal generation . . . . . . . . . . . . . . . . . 214 11.4.4.3 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 11.5 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216 11.6 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 11.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 11.7.1 tima clock pin (pte3/ tclka) . . . . . . . . . . . . . . . . . . . . . 217 11.7.2 tima channel i/o pins (pte4/tch0a?pte7/tch3a) . . . . . . . . . . . . . . . . . . . 217 11.8 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 11.8.1 tima status an d control register . . . . . . . . . . . . . . . . . . . 218 11.8.2 tima counter registers. . . . . . . . . . . . . . . . . . . . . . . . . . .221 11.8.3 tima counter modulo registers . . . . . . . . . . . . . . . . . . . . 222 11.8.4 tima channel status and control registers . . . . . . . . . . . 222 11.8.5 tima channel registers . . . . . . . . . . . . . . . . . . . . . . . . . . 227 advance information mc68hc908mr24 ? rev. 4.1 204 timer interface a (tima) freescale semiconductor timer interface a (tima) 11.2 introduction this section describes the timer inte rface module a (tima). the tima is a 4-channel timer that provides a ti ming reference with input capture, output compare, and pulse-wid th modulator functions. figure 11-1 is a block diagram of the tima. 11.3 features features of t he tima include: four input capture/out put compare channels: ? rising-edge, falling-edge, or any-edge input capture trigger ? set, clear, or toggle output compare action buffered and unbuffered pulse- width modulator (pwm) signal generation programmable tima clock input: ? 7-frequency internal bus cl ock prescaler selection ? external tima clock inpu t (4-mhz maximum frequency) free-running or modul o up-count operation toggle any channel pin on overflow tima counter stop and reset bits timer interface a (tima) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor timer interface a (tima) 205 figure 11-1. tima block diagram pte3/tclka prescaler prescaler select tclk internal 16-bit comparator ps2 ps1 ps0 16-bit comparator 16-bit latch tch0h:tch0l ms0a els0b els0a pte4 tof toie inter- channel 0 tmodh:tmodl trst tstop tov0 ch0ie ch0f ch0max ms0b 16-bit counter bus clock pte4/tch0a pte5/tch1a pte6/tch2a pte7/tch3a logic rupt logic inter- rupt logic 16-bit comparator 16-bit latch tch1h:tch1l ms1a els1b els1a pte5 channel 1 tov1 ch1ie ch1f ch1max logic inter- rupt logic 16-bit comparator 16-bit latch tch2h:tch2l ms2a els2b els2a pte6 channel 2 tov2 ch2ie ch2f ch2max ms2b logic inter- rupt logic 16-bit comparator 16-bit latch tch3h:tch3l els3b els3a pte7 channel 3 tov3 ch3ie ch3f ch3max logic inter- rupt logic ms3a advance information mc68hc908mr24 ? rev. 4.1 206 timer interface a (tima) freescale semiconductor timer interface a (tima) addr. register name bit 7 6 5 4 3 2 1 bit 0 $000e tima status/control register (tasc) see page 218. read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst r reset: 0 0 1 0 0 0 0 0 $000f tima counter register high (tacnth) see page 221. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: r r r r r r r r reset: 0 0 0 0 0 0 0 0 $0010 tima counter register low tacntl) see page 221. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: r r r r r r r r reset: 0 0 0 0 0 0 0 0 $0011 tima counter modulo register high (tamodh) see page 222. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 1 1 1 1 1 1 1 1 $0012 tima counter modulo register low (tamodl) see page 222. read: bit 7 6 5 4 3 2 1 bit 0 write: reset: 1 1 1 1 1 1 1 1 $0013 tima channel 0 status/control register (tasc0) see page 223. read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset: 0 0 0 0 0 0 0 0 $0014 tima channel 0 register high (tach0h) see page 228. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0015 tima channel 0 register low (tach0l) see page 228. read: bit 7 6 5 4 3 2 1 bit 0 write: reset: indeterminate after reset $0016 tima channel 1 status/control register (tasc1) see page 223. read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 r reset: 0 0 0 0 0 0 0 0 r= reserved figure 11-2. tim i/o register summary timer interface a (tima) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor timer interface a (tima) 207 $0017 tima channel 1 register high (tach1h) see page 228. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0018 tima channel 1 register low (tach1l) see page 228. read: bit 7 6 5 4 3 2 1 bit 0 write: reset: indeterminate after reset $0019 tima channel 2 status/control register (tasc2) see page 223. read: ch2f ch2ie ms2b ms2a els2b els2a tov2 ch2max write: 0 reset: 0 0 0 0 0 0 0 0 $001a tima channel 2 register high (tach2h) see page 228. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $001b tima channel 2 register low (tach2l) see page 228. read: bit 7 6 5 4 3 2 1 bit 0 write: reset: indeterminate after reset $001c tima channel 3 status/control register (tasc3) see page 228. read: ch3f ch3ie 0 ms3a els3b els3a tov3 ch3max write: 0 r reset: 0 0 0 0 0 0 0 0 $001d tima channel 3 register high (tach3h) see page 228. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $001e tima channel 3 register low (tach3l) see page 228. read: bit 7 6 5 4 3 2 1 bit 0 write: reset: indeterminate after reset addr. register name bit 7 6 5 4 3 2 1 bit 0 r= reserved figure 11-2. tim i/o regi ster summary (continued) advance information mc68hc908mr24 ? rev. 4.1 208 timer interface a (tima) freescale semiconductor timer interface a (tima) 11.4 functional description figure 11-1 shows the tima structure. the central component of the tima is the 16-bit tima counter that can operate as a free-running counter or a modulo up-c ounter. the tima counter provides the timing reference for the input capture and output compare functions. the tima counter modulo registers, tamo dh?tamodl, control the modulo value of the tima count er. software can read the tima counter value at any time without affect ing the counting sequence. the four tima channels are progr ammable independently as input capture or output compare channels. 11.4.1 tima counter prescaler the tima clock source can be one of the seven prescaler outputs or the tima clock pin, pte3/tclka. the prescaler generat es seven clock rates from the internal bus clock. the prescaler se lect bits, ps[2:0], in the tima status and co ntrol register select the tima clock source. 11.4.2 input capture an input capture function has three basic parts: edge select logic input capture latch 16-bit counter two 8-bit registers, which make up the 16-bit input capt ure register, are used to latch the va lue of the free-runni ng counter after the corresponding input captur e edge detector senses a defined transition. the polarity of the acti ve edge is programmabl e. the level transition which triggers the counter transfer is defined by the corresponding input edge bits (elsxb and elsxa in tasc 0?tasc3 control registers with x referring to the active channel number). when an active edge occurs on the pin of an input capture channel, t he tima latches t he contents of the tima counter into the tima channel registers, tachxh?tachxl. input captures can generate tima cpu in terrupt requests. software can timer interface a (tima) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor timer interface a (tima) 209 determine that an input capture event has occu rred by enabling input capture interrupts or by pol ling the stat us flag bit. the result obtained by an input captur e will be two more than the value of the free-running count er on the rising edge of the internal bus clock preceding the external transition. th is delay is required for internal synchronization. the free-running c ounter contents are transfe rred to the tima channel status and control regist er (tachxh? tachxl, see 11.8.5 tima channel registers ) on each proper signal tr ansition regardless of whether the tima channel fl ag (ch0f?ch3f in tasc0?tasc3 registers) is set or clea r. when the status flag is set, a cpu interrupt is generated if enabled. t he value of the count latc hed or ?captured? is the time of the event. because this valu e is stored in the input capture register 2 bus cycles afte r the actual ev ent occurs, user software can respond to this event at a later time and determine the actual time of the event. however, this must be done pr ior to another input capture on the same pin; otherwise, the previous time va lue will be lost. by recording the time s for successive edges on an incoming signal, software can determine the period and/or pulse width of the signal. to measure a period, two successive edges of t he same polarity are captured. to measure a pulse width, two alternate pol arity edges are captured. software should track t he overflows at the 16-bit module counter to extend its range. another use for the input capture function is to establish a time reference. in this case , an input capture function is used in conjunction with an output compare function. fo r example, to activate an output signal a specified number of clock cycles after det ecting an input event (edge), use the input capture function to record the time at which the edge occurred. a number co rresponding to the desir ed delay is added to this captured value an d stored to an output co mpare register (see 11.8.5 tima channel registers ). because both input captures and output compares are referenced to the same 16-bit m odulo counter, the delay can be controlled to the resoluti on of the counte r independent of software latencies. reset does not affect t he contents of the input capture channel registers. advance information mc68hc908mr24 ? rev. 4.1 210 timer interface a (tima) freescale semiconductor timer interface a (tima) 11.4.3 output compare with the output compare function, the tima can generate a periodic pulse with a progr ammable polarity, duration, and frequency. when the counter reaches the value in the r egisters of an output compare channel, the tima can se t, clear, or toggle the channel pin. output compares can generate tima cpu interrupt requests. 11.4.3.1 unbuffer ed output compare any output compare channel can generate unbuffered output compare pulses as described in 11.4.3 output compare . the pulses are unbuffered because changing the output compare value requires writing the new value over the ol d value currently in th e tima channel registers. an unsynchronized write to the tima channel registers to change an output compare value could cause incorrect operati on for up to two counter overflow periods. for exampl e, writing a new value before the counter reaches the old value but after the c ounter reaches the new value prevents any compare during that counter overflow period. also, using a tima overflow interrupt rout ine to write a new , smaller output compare value may caus e the compare to be missed. the tima may pass the new value bef ore it is written. use this method to synchronize unbuffered changes in the output compare value on channel x: when changing to a smaller va lue, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current output compare pulse . the interrupt routine has until the end of the counter overflow period to write the new value. when changing to a larger output compare val ue, enable channel x tima overflow inte rrupts and write the new value in the tima overflow interrupt routine. the tima overflow interrupt occurs at the end of the cu rrent counter overflow per iod. writing a larger value in an output co mpare interrupt routin e (at the end of the current pulse) could c ause two output compar es to occur in the same counter overflow period. timer interface a (tima) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor timer interface a (tima) 211 11.4.3.2 buffered output compare channels 0 and 1 can be linked to form a buffered output compare channel whose output appe ars on the pte4/tch0 a pin. the tima channel registers of th e linked pair alternatel y control the output. setting the ms0b bit in tima channe l 0 status and control register (tasc0) links channel 0 and channel 1. the output compare value in the tima channel 0 regist ers initially controls the output on the pte4/tch0a pin. writing to the tima channel 1 registers enables the tima channel 1 registers to synchr onously control the output after the tima overflows. at each subseque nt overflow, the tima channel registers (0 or 1) that control the output are t he ones written to last. tasc0 controls and monitors the buf fered output compar e function, and tima channel 1 status and control regi ster (tasc1) is unused. while the ms0b bit is set, the channel 1 pin, pte5/tch1a, is available as a general-purpose i/o pin. channels 2 and 3 can be linked to form a buffered output compare channel whose output appe ars on the pte6/tch2 a pin. the tima channel registers of th e linked pair alternatel y control the output. setting the ms2b bit in tima channe l 2 status and control register (tasc2) links channel 2 and channel 3. the output compare value in the tima channel 2 regist ers initially controls the output on the pte6/tch2a pin. writing to the tima channel 3 registers enables the tima channel 3 registers to synchr onously control the output after the tima overflows. at each subseque nt overflow, the tima channel registers (2 or 3) that control the output are t he ones written to last. tasc2 controls and monitors the buf fered output compar e function, and tima channel 3 status and control regi ster (tasc3) is unused. while the ms2b bit is set, the channel 3 pin, pte7/tch3a, is available as a general-purpose i/o pin. note: in buffered output compare operati on, do not write new output compare values to the currently active channel registers. writing to the active channel registers is the same as generating unbuffered output compares. advance information mc68hc908mr24 ? rev. 4.1 212 timer interface a (tima) freescale semiconductor timer interface a (tima) 11.4.4 pulse-widt h modulation (pwm) by using the toggle-on-overflow f eature with an output compare channel, the tima can generate a pwm signal. the value in the tima counter modulo registers determi nes the period of th e pwm signal. the channel pin toggles when the counter reaches the value in the tima counter modulo registers. the time between ov erflows is the period of the pwm signal. as figure 11-3 shows, the output compare value in the tima channel registers determines t he pulse width of the pwm signal. the time between overflow and output compare is the pulse width. program the tima to clear the channel pin on output compare if the state of the pwm pulse is logic 1. program the tima to set the pin if the state of the pwm pulse is logic 0. figure 11-3. pwm peri od and pulse width the value in the tima counter m odulo registers and the selected prescaler output determines the frequency of the pwm output. the frequency of an 8-bit pwm signal is va riable in 256 in crements. writing $00ff (255) to the tima counter modulo regi sters produces a pwm period of 256 times the in ternal bus clock period if the prescaler select value is $000 (see 11.8.1 tima status a nd control register ). the value in the tima channel regist ers determines the pulse width of the pwm output. the puls e width of an 8-bit pwm signal is variable in 256 increments. writing $0080 (128) to the tima channel registers produces a duty cycle of 128/256 or 50 percent. ptex/tchx period pulse width overflow overflow overflow output compare output compare output compare timer interface a (tima) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor timer interface a (tima) 213 11.4.4.1 unbuffered pwm signal generation any output compare channel can generate unbuffered pwm pulses as described in 11.4.4 pulse-width modulation (pwm) . the pulses are unbuffered because changing the pulse width requires writing the new pulse width value over t he value currently in t he tima channel registers. an unsynchronized write to the tima channel registers to change a pulse width value coul d cause incorrect operat ion for up to two pwm periods. for example, writing a ne w value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that pwm period. also, using a ti ma overflow interrupt routine to write a new, smaller pulse width val ue may cause the compare to be missed. the ti ma may pass the new value be fore it is written to the tima channel registers. use this method to synchronize unbu ffered changes in the pwm pulse width on channel x: when changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current pu lse. the interrupt routi ne has until the end of the pwm period to write the new value. when changing to a longer pulse width, enable channel x tima overflow interrupts and write the new value in the tima overflow interrupt routine. the tima overflow interrupt occurs at the end of the current pwm period. writin g a larger value in an output compare interrupt routine (at t he end of the curr ent pulse) could cause two output compares to occur in the same pwm period. note: in pwm signal generation , do not program the pw m channel to toggle on output compare. toggling on out put compare prevents reliable 0 percent duty cycle gener ation and removes the ability of the channel to self-correct in the ev ent of software error or noise. toggling on output compare also can cause incorr ect pwm signal generation when changing the pwm pulse width to a new, much larger value. advance information mc68hc908mr24 ? rev. 4.1 214 timer interface a (tima) freescale semiconductor timer interface a (tima) 11.4.4.2 buffered pwm signal generation channels 0 and 1 can be linked to form a buffered pwm channel whose output appears on the pte4 /tch0a pin. the tima channel registers of the linked pair alternately contro l the pulse width of the output. setting the ms0b bit in tima channe l 0 status and control register (tasc0) links channel 0 and channel 1. the tima channel 0 registers initially control the pulse width on the pte4/tch0a pin. writing to the tima channel 1 regist ers enables the tima channel 1 regi sters to synchronously control the pulse width at the beginning of the next pwm period. at each subsequent overfl ow, the tima channel registers (0 or 1) that control the pulse width are the ones written to last. tasc0 controls and monitors the buffer ed pwm function, and tima channel 1 status and control register (tasc1) is unused. while the ms0b bit is set, the channel 1 pin, pte5/tch1a, is available as a general-purpose i/o pin. channels 2 and 3 can be linked to form a buffered pwm channel whose output appears on the pte6 /tch2a pin. the tima channel registers of the linked pair alternately contro l the pulse width of the output. setting the ms2b bit in tima channe l 2 status and control register (tasc2) links channel 2 and channel 3. the tima channel 2 registers initially control the pulse width on the pte6/tch2a pin. writing to the tima channel 3 regist ers enables the tima channel 3 regi sters to synchronously control the pulse width at the beginning of the next pwm period. at each subsequent overfl ow, the tima channel registers (2 or 3) that control t he pulse width are written to last. tasc2 controls and monitors the buffer ed pwm function, and ti ma channel 3 status and control register (tasc3 ) is unused. while the ms2b bit is set, the channel 3 pin, pte7/tch3a, is available as a general-purpose i/o pin. note: in buffered pwm signal gener ation, do not write new pulse width values to the currently active channel registers. writi ng to the acti ve channel registers is the same as gen erating unbuffe red pwm signals. timer interface a (tima) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor timer interface a (tima) 215 11.4.4.3 pwm initialization to ensure correct operation when gen erating unbuffered or buffered pwm signals, use this initialization procedure: 1. in the tima status and control register (tasc): a. stop the tima counter by sett ing the tima stop bit, tstop. b. reset the tima counter by sett ing the tima reset bit, trst. 2. in the tima counter modulo r egisters (tamodh?tamodl), write the value for the required pwm period. 3. in the tima channel x registers (tachxh ?tachxl), write the value for the requ ired pulse width. 4. in tima channel x status and contro l register (tscx): a. write 0:1 (for unbuffered outp ut compare or pwm signals) or 1:0 (for buffered output com pare or pwm si gnals) to the mode select bits, msxb?msxa. (see table 11-2 .) b. write 1 to the toggle- on-overflow bit, tovx. c. write 1:0 (to clear output on co mpare) or 1:1 (to set output on compare) to the edge/level se lect bits, elsxb?elsxa. the output action on compare must force the output to the complement of the pulse width level. (see table 11-2 .) note: in pwm signal generation , do not program the pw m channel to toggle on output compare. toggling on out put compare prevents reliable 0 percent duty cycle gener ation and removes the ability of the channel to self-correct in the ev ent of software error or noise. toggling on output compare can also cause incorr ect pwm signal generation when changing the pwm pulse width to a new, much larger value. 5. in the tima stat us control register (tasc) , clear the ti ma stop bit, tstop. setting ms0b links chann els 0 and 1 and configur es them for buffered pwm operation. the tima channel 0 registers (tach0h?tach0l) initially control the buff ered pwm output. tima st atus control register 0 (tasc0) controls and monitors the pwm signal fr om the linked channels. ms0b takes pr iority over ms0a. advance information mc68hc908mr24 ? rev. 4.1 216 timer interface a (tima) freescale semiconductor timer interface a (tima) setting ms2b links chann els 2 and 3 and configur es them for buffered pwm operation. the tima channel 2 registers (tach2h?tach2l) initially control the pwm output. tima status cont rol register 2 (tasc2) controls and monitors the pwm signal from the linked channels. ms2b takes priority over ms2a. clearing the toggle-on-overflow bit, tovx, inhibits output toggles on tima overflows. subsequen t output compares try to force the output to a state it is already in and have no effect. the resu lt is a 0 percent duty cycle output. setting the channel x maximum dut y cycle bit (chxm ax) and clearing the tovx bit generates a 100 percent duty cycle output. (see 11.8.4 tima channel status and control registers .) 11.5 interrupts these tima sources can generate inte rrupt requests: tima overflow flag (tof) ? the to f bit is set when the tima counter value rolls over to $0000 after matching t he value in the tima counter modulo registers. the tima overflow interrupt enable bit, toie, enables tima overflow cpu interrupt requests. tof and toie are in the tima status a nd control register. tima channel flags (ch3f?ch0f) ? the chxf bit is set when an input capture or output compar e occurs on channel x. channel x tima cpu interrupt r equests are controlled by the channel x interrupt enable bit, chxie. 11.6 wait mode the wait instruction pu ts the mcu in low pow er-consumption standby mode. the tima remains active af ter the execution of a wait instruction. in wait mode, the tima r egisters are not accessib le by the cpu. any enabled cpu interrupt reque st from the tima can bring the mcu out of wait mode. timer interface a (tima) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor timer interface a (tima) 217 if tima functions are not requir ed during wait mode, reduce power consumption by stoppi ng the tima before ex ecuting the wait instruction. 11.7 i/o signals port e shares five of its pins with the tima: pte3/tclka is an external clock input to the tima prescaler. the four tima channel i/o pins are pte4/tch0a, pte5/tch1a, pte6/tch2a, and pte7/tch3a. 11.7.1 tima clock pin (pte3/tclka) pte3/tclka is an external clock inpu t that can be the clock source for the tima counter instead of the presca led internal bus clock. select the pte3/tclka input by writing logi c 1s to the three prescaler select bits, ps[2:0]. see 11.8.1 tima status and control register . the minimum tclk pulse width, tclk lmin or tclk hmin , is: the maximum tclk frequency is the least: 4 mhz or bus frequency 2. pte3/tclka is availabl e as a general-purpose i/o pin or adc channel when not used as the tima clock input. when the pt e3/tclka pin is the tima clock input, it is an input regardless of the state of the ddre3 bit in data direction register e. 11.7.2 tima chan nel i/o pins (pte4/ tch0a?pte7/tch3a) each channel i/o pin is progr ammable independently as an input capture pin or an output compare pin. pte2/tch0 and pte4/tch2 can be configured as buffer ed output compare or buffered pwm pins. 1 bus frequency ------------------- ------------------ t su + advance information mc68hc908mr24 ? rev. 4.1 218 timer interface a (tima) freescale semiconductor timer interface a (tima) 11.8 i/o registers these input/output (i/o) registers c ontrol and monitor tima operation: tima status and cont rol register (tasc) tima control regist ers (tacnth?tacntl) tima counter modulo regi sters (tamodh?tamodl) tima channel status and contro l registers (tasc0, tasc1, tasc2, and tasc3) tima channel registers (ta ch0h?tach0l, tach1h?tach1l, tach2h?tach2l, and tach3h?tach3l) 11.8.1 tima status and control register the tima status and control register: enables tima overflow interrupts flags tima overflows stops the tima counter resets the tima counter prescales the tima counter clock tof ? tima overflow flag this read/write flag is set when the tima counter resets to $0000 after reaching the modulo value program med in the tima counter modulo registers. clear tof by reading the tima status and control register address: $000e bit 7654321bit 0 read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst r reset:00100000 r= reserved figure 11-4. tima status and control register (tasc) timer interface a (tima) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor timer interface a (tima) 219 when tof is set and then writing a logic 0 to tof. if another tima overflow occurs before the clear ing sequence is complete, then writing logic 0 to tof has no ef fect. therefore, a tof interrupt request cannot be lost du e to inadvertent clea ring of tof. reset clears the tof bit. writing a logic 1 to tof has no effect. 1 = tima counter ha s reached modulo value. 0 = tima counter has not reached modulo value. toie ? tima overflow interrupt enable bit this read/write bit enables tima overflow interr upts when the tof bit becomes set. reset cl ears the toie bit. 1 = tima overflow interrupts enabled 0 = tima overflow interrupts disabled tstop ? tima stop bit this read/write bit stop s the tima counter. counting resumes when tstop is cleared. reset sets t he tstop bit, stopping the tima counter until software clears the tstop bit. 1 = tima counter stopped 0 = tima counter active note: do not set the tstop bit before enter ing wait mode if the tima is required to exit wait mode. also w hen the tstop bit is set and the timer is configured for input capture operation, input captures are inhibited until the tstop bit is cleared. trst ? tima reset bit setting this write-only bit resets the tima counte r and the tima prescaler. setting trst has no ef fect on any other registers. counting resumes from $0000 . trst is cleared automatically after the tima counter is re set and always reads as logic 0. reset clears the trst bit. 1 = prescaler and tima counter cleared 0 = no effect note: setting the tstop and trst bits simultaneously stops the tima counter at a value of $0000. advance information mc68hc908mr24 ? rev. 4.1 220 timer interface a (tima) freescale semiconductor timer interface a (tima) ps[2:0] ? prescaler select bits these read/write bits select either the ptd6/atd14/tc lk pin or one of the seven prescaler outputs as t he input to the ti ma counter as table 11-1 shows. reset clear s the ps[2:0] bits. table 11-1. pres caler selection ps[2:0] tima clock source 000 internal bus clock 1 001 internal bus clock 2 010 internal bus clock 4 011 internal bus clock 8 100 internal bus clock 16 101 internal bus clock 32 110 internal bus clock 64 111 pte3/tclka timer interface a (tima) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor timer interface a (tima) 221 11.8.2 tima c ounter registers the two read-only tima counter regist ers contain the high and low bytes of the value in the tima counter . reading the high byte (tacnth) latches the contents of the low byte (tacntl) into a buffer. subsequent reads of tacnth do not affect the latched tacntl value until tacntl is read. reset clears the tima counter registers. setting the tima reset bit (trst) also clears t he tima counter registers. note: if tacnth is read during a break interrupt, be sure to unlatch tacntl by reading tacntl before exiting the break interrupt. otherwise, tacntl retains the value latched during the break. register name and address: tacnth ? $000f bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write:rrrrrrrr reset:00000000 register name and address: tacntl ? $0010 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write:rrrrrrrr reset:00000000 r= reserved figure 11-5. tima counter registers (tacnth and tacntl) advance information mc68hc908mr24 ? rev. 4.1 222 timer interface a (tima) freescale semiconductor timer interface a (tima) 11.8.3 tima counter modulo registers the read/write tima modulo registers contain the modulo value for the tima counter. when the tima counter reaches the m odulo value, the overflow flag (tof) bec omes set, an d the tima counter resumes counting from $0000 at the next cl ock. writing to the high byte (tamodh) inhibits the to f bit and overflow interr upts until the low byte (tamodl) is written. reset sets the tima counter modulo registers. note: reset the tima counter before wr iting to the tima counter modulo registers. 11.8.4 tima channel stat us and control registers each of the tima channel st atus and control registers: flags input captures and output compares enables input capture and output compare interrupts selects input capture, output compare, or pwm operation selects high, low, or t oggling output on output compare register name and address: tamodh ? $0011 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:11111111 register name and address: tamodl ? $0012 bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:11111111 figure 11-6. tima c ounter modulo registers (tamodh and tamodl) timer interface a (tima) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor timer interface a (tima) 223 selects rising edge, fall ing edge, or any edge as the active input capture trigger selects output toggl ing on tima overflow selects 100 percent pwm duty cycle selects buffered or unbuffer ed output compare/pwm operation register name and address: tasc0 ? $0013 bit 7654321bit 0 read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 register name and address: tasc1 ? $0016 bit 7654321bit 0 read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 r reset:00000000 register name and address: tasc2 ? $0019 bit 7654321bit 0 read: ch2f ch2ie ms2b ms2a els2b els2a tov2 ch2max write: 0 reset:00000000 register name and address: tasc3 ? $001c bit 7654321bit 0 read: ch3f ch3ie 0 ms3a els3b els3a tov3 ch3max write: 0 r reset:00000000 r= reserved figure 11-7. ti ma channel status and control regist ers (tasc0?tasc3) advance information mc68hc908mr24 ? rev. 4.1 224 timer interface a (tima) freescale semiconductor timer interface a (tima) chxf ? chann el x flag bit when channel x is an inpu t capture channel, this read/write bit is set when an active edge occurs on the channel x pin. when channel x is an output compare channel, chxf is set when the value in the tima counter registers matche s the value in the ti ma channel x registers. when chxie = 0, clear chxf by re ading tima channel x status and control register with chxf set, a nd then writing a logi c 0 to chxf. if another interrupt request occurs before the clearing sequence is complete, then writing l ogic 0 to chxf has no effect. therefore, an interrupt request cannot be lost due to inadvertent clearing of chxf. reset clears the chxf bit. writing a logic 1 to chxf has no effect. 1 = input capture or out put compare on channel x 0 = no input capture or output compare on channel x chxie ? channel x in terrupt enable bit this read/write bit enabl es tima cpu interrupts on channel x. reset clears the chxie bit. 1 = channel x cpu inte rrupt requests enabled 0 = channel x cpu interr upt requests disabled msxb ? mode select bit b this read/write bit sele cts buffered output co mpare/pwm operation. msxb exists only in the tima c hannel 0 and tima ch annel 2 status and control registers. setting ms0b disables the channel 1 status and control register and reverts tch1a pin to general-purpose i/o. setting ms2b disables the channel 3 status and control register and reverts tch3a pin to general-purpose i/o. reset clears the msxb bit. 1 = buffered output com pare/pwm operation enabled 0 = buffered output compar e/pwm operation disabled timer interface a (tima) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor timer interface a (tima) 225 msxa ? mode select bit a when elsxb:a 00, this read/write bit se lects either input capture operation or unbuffered outp ut compare/pwm operation. see table 11-2 . 1 = unbuffered output compare/pwm operation 0 = input capt ure operation when elsxb:a = 00, this read/write bit selects the in itial output level of the tchxa pin once pwm, input capture, or output compare operation is enabled. see table 11-2 . reset clears the msxa bit. 1 = initial output level low 0 = initial output level high note: before changing a channel function by writing to the msxb or msxa bit, set the tstop and trst bi ts in the tima status and control register (tasc). elsxb and elsxa ? edge/level select bits when channel x is an i nput capture channel, th ese read/write bits control the active edge- sensing logic on channel x. when channel x is an output co mpare channel, elsxb and elsxa control the channel x output beh avior when an output compare occurs. when elsxb and elsxa are both cl ear, channel x is not connected to port e, and pin ptex /tchxa is available as a general-purpose i/o pin. however, channel x is at a state determined by these bits and becomes transparent to the respecti ve pin when pwm, input capture, or output compare mode is enabled. table 11-2 shows how elsxb and elsxa work. reset clears the elsxb and elsxa bits. advance information mc68hc908mr24 ? rev. 4.1 226 timer interface a (tima) freescale semiconductor timer interface a (tima) note: before enabling a tima channel register for input capture operation, make sure that t he ptex/tachx pin is stable for at least two bus clocks. tovx ? toggle-on-overflow bit when channel x is an output compar e channel, this read/write bit controls the behavior of the channel x output when the tima counter overflows. when channel x is an i nput capture channel, tovx has no effect. reset clear s the tovx bit. 1 = channel x pin toggles on tima counter overflow. 0 = channel x pin does not toggl e on tima counter overflow. note: when tovx is set, a tima counter overflow takes precedence over a channel x output compare if bot h occur at the same time. table 11-2. mode, edge, and level selection msxb:msxa elsxb:elsxa mode configuration x0 00 output preset pin under port control; initialize timer output level high x1 00 pin under port control; initialize timer output level low 00 01 input capture capture on rising edge only 00 10 capture on falling edge only 00 11 capture on rising or falling edge 01 01 output compare or pwm toggle output on compare 01 10 clear output on compare 01 11 set output on compare 1x 01 buffered output compare or buffered pwm toggle output on compare 1x 10 clear output on compare 1x 11 set output on compare timer interface a (tima) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor timer interface a (tima) 227 chxmax ? channel x ma ximum duty cycle bit when the tovx bit is at logic 0, setting the chxmax bit forces the duty cycle of buffered a nd unbuffered pwm signal s to 100 percent. as figure 11-8 shows, the chxmax bit takes effect in the cycle after it is set or cleared. also, tovx bit take s effect in the cycl e in which it is set or cleared. the output stays at the 100 percent duty cycle level until the cycle after ch xmax is cleared. figure 11-8. chxmax latency 11.8.5 tima c hannel registers these read/write registers contain t he captured tima c ounter value of the input capture functi on or the output compar e value of the output compare function. the stat e of the tima channel registers after reset is unknown. in input capture mode (m sxb:msxa = 0:0), reading the high byte of the tima channel x registers (tachxh) inhibits input captures until the low byte (tachxl) is read. in output compare mode (msxb:msxa 0:0), writing to the high byte of the tima channel x regist ers (tachxh) inhibits output compares until the low byte (tachxl) is written. output overflow ptex/tchx period chxmax overflow overflow overflow overflow compare output compare output compare output compare tovx advance information mc68hc908mr24 ? rev. 4.1 228 timer interface a (tima) freescale semiconductor timer interface a (tima) register name and address: tach0h ? $0014 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset register name and address: tach0l ? $0015 bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: indeterminate after reset register name and address: tach1h ? $0017 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset register name and address: tach1l ? $0018 bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: indeterminate after reset register name and address: tach2h ? $001a bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset figure 11-9. tima channel registers (tach0h/l?tach3h/l) timer interface a (tima) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor timer interface a (tima) 229 register name and address: tach2l ? $001b bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: indeterminate after reset register name and address: tach3h ? $001d bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset register name and address: tach3l ? $001e bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: indeterminate after reset figure 11-9. tima channel registers (tach0h/l?tach3h/l) (continued) advance information mc68hc908mr24 ? rev. 4.1 230 timer interface a (tima) freescale semiconductor timer interface a (tima) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor timer interface b (timb) 231 advance information ? mc68hc908mr24 section 12. timer interface b (timb) 12.1 contents 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 12.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 12.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232 12.4.1 timb counter prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . .233 12.4.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 12.4.3 output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 12.4.3.1 unbuffered output compare . . . . . . . . . . . . . . . . . . . . . 236 12.4.3.2 buffered output com pare . . . . . . . . . . . . . . . . . . . . . . .237 12.4.4 pulse-width modulatio n (pwm) . . . . . . . . . . . . . . . . . . . . . 238 12.4.4.1 unbuffered pwm sig nal generation . . . . . . . . . . . . . . . 239 12.4.4.2 buffered pwm signal generation . . . . . . . . . . . . . . . . . 240 12.4.4.3 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 12.5 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242 12.6 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 12.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 12.7.1 timb clock pin (ptd4/ atd12) . . . . . . . . . . . . . . . . . . . . . 243 12.7.2 timb channel i/o pins (pte1/tch0b?pte2/tch1b) . . . . . . . . . . . . . . . . . . . 243 12.8 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 12.8.1 timb status an d control register . . . . . . . . . . . . . . . . . . . 244 12.8.2 timb counter registers. . . . . . . . . . . . . . . . . . . . . . . . . . .247 12.8.3 timb counter modulo registers . . . . . . . . . . . . . . . . . . . . 248 12.8.4 timb channel status and control registers . . . . . . . . . . . 249 12.8.5 timb channel registers . . . . . . . . . . . . . . . . . . . . . . . . . . 253 advance information mc68hc908mr24 ? rev. 4.1 232 timer interface b (timb) freescale semiconductor timer interface b (timb) 12.2 introduction this section describes the timer inte rface module b (timb). the timb is a 2-channel timer that provides a ti ming reference with input capture, output compare, and pulse-wid th modulation functions. figure 12-1 is a block diagram of the timb. note: the timb module is not available in the 56-pin shrink dual in-line package (sdip). 12.3 features features of t he timb include: two input capture/ou tput compare channels: ? rising-edge, falling-edge, or any-edge input capture trigger ? set, clear, or toggle output compare action buffered and unbuffered pulse- width modulation (pwm) signal generation programmable timb clock input: ? 7-frequency internal bus cl ock prescaler selection ? external timb clock inpu t (4-mhz maximum frequency) free-running or modul o up-count operation toggle any channel pin on overflow timb counter stop and reset bits 12.4 functional description figure 12-1 shows the timb structure. the central component of the timb is the 16-bit timb counter that can operate as a free-running counter or a modulo up-c ounter. the timb counter provides the timing reference for the input capture and output compare functions. the timb counter modulo registers, tbmo dh?tbmodl, control the modulo timer interface b (timb) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor timer interface b (timb) 233 value of the timb count er. software can read the timb counter value at any time without affect ing the counting sequence. figure 12-1. timb block diagram the two timb channels are progra mmable independently as input capture or output compare channels. note: the timb module is not availa ble in the 56-pin sdip. 12.4.1 timb counter prescaler the timb clock source can be one of the seven prescaler outputs or the timb clock pin, ptd4/atd12. t he prescaler generates seven clock rates from the internal bus clock. the prescaler se lect bits, ps[2:0], in the timb status and co ntrol register select the timb clock source. prescaler prescaler select tclk internal 16-bit comparator ps2 ps1 ps0 16-bit comparator 16-bit latch tch0h:tch0l ms0a els0b els0a pte1 tof toie inter- channel 0 tmodh:tmodl trst tstop tov0 ch0ie ch0f ch0max ms0b 16-bit counter bus clock pte0/tclkb pte1/tch0b pte2/tch1b logic rupt logic inter- rupt logic 16-bit comparator 16-bit latch tch1h:tch1l ms1a els1b els1a pte2 channel 1 tov1 ch1ie ch1f ch1max logic inter- rupt logic advance information mc68hc908mr24 ? rev. 4.1 234 timer interface b (timb) freescale semiconductor timer interface b (timb) addr. register name bit 7 6 5 4 3 2 1 bit 0 $0051 timb status/control register (tbsc) see page 244. read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst r reset: 0 0 1 0 0 0 0 0 $0052 timb counter register high (tbcnth) see page 247. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: r r r r r r r r reset: 0 0 0 0 0 0 0 0 $0053 timb counter register low (tbcntl) see page 247. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: r r r r r r r r reset: 0 0 0 0 0 0 0 0 $0054 timb counter modulo register high (tbmodh) see page 248. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 1 1 1 1 1 1 1 1 $0055 timb counter modulo register low (tbmodl) see page 248. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 1 1 1 1 1 1 1 1 $0056 timb channel 0 status/control register (tbsc0) see page 249. read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset: 0 0 0 0 0 0 0 0 $0057 timb channel 0 register high (tbch0h) see page 254. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset $0058 timb channel 0 register low (tbch0l) see page 254. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset $0059 timb channel 1 status/control register (tbsc1) see page 249. read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 r reset: 0 0 0 0 0 0 0 0 $005a timb channel 1 register high (tbch1h) see page 254. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset $005b timb channel 1 register low (tbch1l) see page 254. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset r= reserved figure 12-2. timb i/ o register summary timer interface b (timb) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor timer interface b (timb) 235 12.4.2 input capture an input capture function has three basic parts: edge select logic input capture latch 16-bit counter two 8-bit registers, which make up the 16-bit input capt ure register, are used to latch the va lue of the free-runni ng counter after the corresponding input captur e edge detector senses a defined transition. the polarity of the acti ve edge is programmabl e. the level transition which triggers the counter transfer is defined by the corresponding input edge bits (elsxb and elsxa in tbsc 0?tbsc1 control registers with x referring to the active channel number). when an active edge occurs on the pin of an input capture channel, t he timb latches t he contents of the timb counter into the timb channel registers, tchxh?tchxl. input captures can generate timb cpu in terrupt requests. software can determine that an input capture event has occu rred by enabling input capture interrupts or by pol ling the stat us flag bit. the result obtained by an input captur e will be two more than the value of the free-running count er on the rising edge of the internal bus clock preceding the external transition. th is delay is required for internal synchronization. the free-running c ounter contents are transfe rred to the timb channel status and control regist er (tbchxh? tbchxl, see 12.8.5 timb channel registers ) on each proper signal tr ansition regardless of whether the timb channel fl ag (ch0f?ch1f in tbsc0?tbsc1 registers) is set or clea r. when the status flag is set, a cpu interrupt is generated if enabled. t he value of the count latc hed or ?captured? is the time of the event. because this valu e is stored in the input capture register 2 bus cycles afte r the actual ev ent occurs, user software can respond to this event at a later time and determine the actual time of the event. however, this must be done pr ior to another input capture on the same pin; otherwise, the previous time va lue will be lost. by recording the time s for successive edges on an incoming signal, software can determine the period and/or pulse width of the signal. to advance information mc68hc908mr24 ? rev. 4.1 236 timer interface b (timb) freescale semiconductor timer interface b (timb) measure a period, two successive edges of t he same polarity are captured. to measure a pulse width, two alternate pol arity edges are captured. software should track t he overflows at the 16-bit module counter to extend its range. another use for the input capture function is to establish a time reference. in this case , an input capture function is used in conjunction with an output compare function. fo r example, to activate an output signal a specified number of clock cycles after det ecting an input event (edge), use the input capture function to record the time at which the edge occurred. a number co rresponding to the desir ed delay is added to this captured value an d stored to an output co mpare register (see 12.8.5 timb channel registers ). because both input captures and output compares are referenced to the same 16-bit m odulo counter, the delay can be controlled to the resoluti on of the counte r independent of software latencies. reset does not affect the contents of the input capture channel register (tbchxh?tbchxl). 12.4.3 output compare with the output compare function, the timb can generate a periodic pulse with a progr ammable polarity, duration, and frequency. when the counter reaches the value in the r egisters of an output compare channel, the timb can se t, clear, or toggle the channel pin. output compares can generate timb cpu interrupt requests. 12.4.3.1 unbuffer ed output compare any output compare channel can generate unbuffered output compare pulses as described in 12.4.3 output compare . the pulses are unbuffered because changing the output compare value requires writing the new value over the ol d value currently in th e timb channel registers. an unsynchronized write to the timb channel registers to change an output compare value could cause incorrect operati on for up to two counter overflow periods. for exampl e, writing a new value before the counter reaches the old value but after the c ounter reaches the new timer interface b (timb) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor timer interface b (timb) 237 value prevents any compare during that counter overflow period. also, using a timb overflow interrupt rout ine to write a new , smaller output compare value may caus e the compare to be missed. the timb may pass the new value bef ore it is written. use this method to synchronize unbuffered changes in the output compare value on channel x: when changing to a smaller va lue, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current output compare pulse . the interrupt routine has until the end of the counter overflow period to write the new value. when changing to a larger output compare val ue, enable channel x timb overflow inte rrupts and write the new value in the timb overflow interrupt routine. the timb overflow interrupt occurs at the end of the cu rrent counter overflow per iod. writing a larger value in an output co mpare interrupt routin e (at the end of the current pulse) could c ause two output compar es to occur in the same counter overflow period. 12.4.3.2 buffered output compare channels 0 and 1 can be linked to form a buffered output compare channel whose output appe ars on the pte1/tch0 b pin. the timb channel registers of th e linked pair alternatel y control the output. setting the ms0b bit in timb channe l 0 status and control register (tbsc0) links channel 0 and channel 1. the output compare value in the timb channel 0 regist ers initially controls the output on the pte1/tch0b pin. writing to the timb channel 1 registers enables the timb channel 1 registers to synchr onously control the output after the timb overflows. at each subseque nt overflow, the timb channel registers (0 or 1) that control the output are the ones written to last. tsc0 controls and monitors the buffered output compar e function, and timb channel 1 status and cont rol register (tbsc1) is unused. while the ms0b bit is set, the channel 1 pin, pte2/tch1b, is available as a general-purpose i/o pin. advance information mc68hc908mr24 ? rev. 4.1 238 timer interface b (timb) freescale semiconductor timer interface b (timb) note: in buffered output compare operati on, do not write new output compare values to the currently active channel registers. writing to the active channel registers is the same as generating unbuffered output compares. 12.4.4 pulse-widt h modulation (pwm) by using the toggle-on-overflow f eature with an output compare channel, the timb can generate a pwm signal. the value in the timb counter modulo registers determi nes the period of th e pwm signal. the channel pin toggles when the counter reaches the value in the timb counter modulo registers. the time between ov erflows is the period of the pwm signal. as figure 12-3 shows, the output compare value in the timb channel registers determines t he pulse width of the pwm signal. the time between overflow and output compare is the pulse width. program the timb to clear the channel pin on output compare if the state of the pwm pulse is logic 1. program the timb to set the pin if the state of the pwm pulse is logic 0. figure 12-3. pwm peri od and pulse width ptex/tchx period pulse width overflow overflow overflow output compare output compare output compare timer interface b (timb) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor timer interface b (timb) 239 the value in the timb counter m odulo registers and the selected prescaler output determines the frequency of the pwm output. the frequency of an 8-bit pwm signal is va riable in 256 in crements. writing $00ff (255) to the timb counter modulo regi sters produces a pwm period of 256 times the in ternal bus clock period if the prescaler select value is $000 (see 12.8.1 timb status a nd control register ). the value in the timb channel regist ers determines the pulse width of the pwm output. the puls e width of an 8-bit pwm signal is variable in 256 increments. writing $0080 (128) to the timb channel registers produces a duty cycle of 128/256 or 50 percent. 12.4.4.1 unbuffered pwm signal generation any output compare channel can generate unbuffered pwm pulses as described in 12.4.4 pulse-width modulation (pwm) . the pulses are unbuffered because changing the pulse width requires writing the new pulse width value over t he value currently in t he timb channel registers. an unsynchronized write to the timb channel registers to change a pulse width value coul d cause incorrect operat ion for up to two pwm periods. for example, writing a ne w value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that pwm period. also, using a ti mb overflow interrupt routine to write a new, smaller pulse width val ue may cause the compare to be missed. the ti mb may pass the new value be fore it is written to the timb channel registers. use this method to synchronize unbu ffered changes in the pwm pulse width on channel x: when changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current pu lse. the interrupt routi ne has until the end of the pwm period to write the new value. when changing to a longer pulse width, enable channel x timb overflow interrupts and write the new value in the timb overflow interrupt routine. the timb overflow interrupt occurs at the end of advance information mc68hc908mr24 ? rev. 4.1 240 timer interface b (timb) freescale semiconductor timer interface b (timb) the current pwm period. writin g a larger value in an output compare interrupt routine (at t he end of the curr ent pulse) could cause two output compares to occur in the same pwm period. note: in pwm signal generation , do not program the pw m channel to toggle on output compare. toggling on out put compare prevents reliable 0 percent duty cycle gener ation and removes the ability of the channel to self-correct in the ev ent of software error or noise. toggling on output compare also can cause incorr ect pwm signal generation when changing the pwm pulse width to a new, much larger value. 12.4.4.2 buffered pwm signal generation channels 0 and 1 can be linked to form a buffered pwm channel whose output appears on the pte1 /tch0b pin. the timb channel registers of the linked pair alternately contro l the pulse width of the output. setting the ms0b bit in timb channe l 0 status and control register (tbsc0) links channel 0 and channel 1. the timb channel 0 registers initially control the pulse width on the pte1/tch0b pin. writing to the timb channel 1 regist ers enables the timb channel 1 regi sters to synchronously control the pulse width at the beginning of the next pwm period. at each subsequent overfl ow, the timb channel registers (0 or 1) that control the pulse width are the ones written to last. tbsc0 controls and monitors the buffer ed pwm function, and timb channel 1 status and control register (tbsc1) is unused. while the ms0b bit is set, the channel 1 pin, pte2/tch1b, is available as a general-purpose i/o pin. note: in buffered pwm signal gener ation, do not write new pulse width values to the currently active channel registers. writi ng to the acti ve channel registers is the same as gen erating unbuffe red pwm signals. timer interface b (timb) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor timer interface b (timb) 241 12.4.4.3 pwm initialization to ensure correct operation when gen erating unbuffered or buffered pwm signals, use this initialization procedure: 1. in the timb status and control register (tbsc): a. stop the timb counter by sett ing the timb stop bit, tstop. b. reset the timb counter by sett ing the timb reset bit, trst. 2. in the timb counter modulo r egisters (tbmodh?tbmodl), write the value for the required pwm period. 3. in the timb channel x registers (tbchxh ?tbchxl), write the value for the requ ired pulse width. 4. in timb channel x status and contro l register (tbscx): a. write 0:1 (for unbuffered outp ut compare or pwm signals) or 1:0 (for buffered output com pare or pwm si gnals) to the mode select bits, msxb?msxa. (see table 12-2 .) b. write 1 to the toggle- on-overflow bit, tovx. c. write 1:0 (to clear output on co mpare) or 1:1 (to set output on compare) to the edge/level se lect bits, elsxb?elsxa. the output action on compare must force the output to the complement of the pulse width level. (see table 12-2 .) note: in pwm signal generation , do not program the pw m channel to toggle on output compare. toggling on out put compare prevents reliable 0 percent duty cycle gener ation and removes the ability of the channel to self-correct in the ev ent of software error or noise. toggling on output compare can also cause incorr ect pwm signal generation when changing the pwm pulse width to a new, much larger value. 5. in the timb stat us control register (tbsc) , clear the ti mb stop bit, tstop. setting ms0b links chann els 0 and 1 and configur es them for buffered pwm operation. the timb channel 0 registers (tbch0h?tbch0l) initially control the buff ered pwm output. timb st atus control register 0 (tbsc0) controls and monitors the pwm signal fr om the linked channels. ms0b takes pr iority over ms0a. advance information mc68hc908mr24 ? rev. 4.1 242 timer interface b (timb) freescale semiconductor timer interface b (timb) clearing the toggle-on-overflow bit, tovx, inhibits output toggles on timb overflows. subsequen t output compares try to force the output to a state it is already in and have no ef fect. the result is a 0 percent duty cycle output. setting the channel x maximum dut y cycle bit (chxm ax) and clearing the tovx bit generates a 100 percent duty cycle output. (see 12.8.4 timb channel status and control registers .) 12.5 interrupts these timb sources can generate inte rrupt requests: timb overflow flag (tof) ? the to f bit is set when the timb counter value rolls over to $0000 after matching t he value in the timb counter modulo registers. the timb overflow interrupt enable bit, toie, enables timb overflow cpu interrupt requests. tof and toie are in the timb status a nd control register. timb channel flags (ch1f?ch0f) ? the chxf bit is set when an input capture or output compar e occurs on channel x. channel x timb cpu interrupt r equests are controlled by the channel x interrupt enable bit, chxie. 12.6 wait mode the wait instruction puts the mc u in low-power standby mode. the timb remains active af ter the execution of a wait instruction. in wait mode, the timb r egisters are not accessib le by the cpu. any enabled cpu interrupt reque st from the timb can bring the mcu out of wait mode. if timb functions are not requir ed during wait mode, reduce power consumption by stoppi ng the timb before ex ecuting the wait instruction. timer interface b (timb) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor timer interface b (timb) 243 12.7 i/o signals port e shares three of its pins with the timb: ptd4/atd12 is an external clock input to the ti mb prescaler. the two timb channel i/o pins are pte1/tch0b and pte2/tch1b. 12.7.1 timb clock pin (ptd4/atd12) ptd4/atd12 is an external clock input that can be the clock source for the timb counter instead of the presca led internal bus clock. select the ptd4/atd12 input by writing logi c 1s to the three pr escaler select bits, ps[2:0]. see 12.8.1 timb status and control register . the minimum tclk pulse width, tclk lmin or tclk hmin , is: the maximum tclk frequency is the least: 4 mhz or bus frequency 2. ptd4/atd12 is avail able as a general-purpose i/o pin or adc channel when not used as the timb clock input. when the pt d4/atd12 pin is the timb clock input, it is an input regardless of the state of the ddre0 bit in data direction register e. 12.7.2 timb chan nel i/o pins (pte1/ tch0b?pte2/tch1b) each channel i/o pin is progr ammable independently as an input capture pin or an output compare pin. pte1/tch0b and pte2/tch1b can be configured as buff ered output compare or buffered pwm pins. 1 bus frequency ------------------- ------------------ t su + advance information mc68hc908mr24 ? rev. 4.1 244 timer interface b (timb) freescale semiconductor timer interface b (timb) 12.8 i/o registers these input/output (i/o) registers c ontrol and monitor timb operation: timb status and cont rol register (tbsc) timb control regist ers (tbcnth?tbcntl) timb counter modulo regi sters (tbmodh?tbmodl) timb channel status and contro l registers (t bsc0 and tbsc1) timb channel registers (tbch0h?tbch0l and tbch1h?tbch1l) 12.8.1 timb status and control register the timb status and control register: enables timb overflow interrupts flags timb overflows stops the timb counter resets the timb counter prescales the timb counter clock tof ? timb overflow flag this read/write flag is set when the timb counter resets to $0000 after reaching the modulo value program med in the timb counter modulo registers. clear tof by reading the timb status and control register address: $0051 bit 7654321bit 0 read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst r reset:00100000 r= reserved figure 12-4. timb status and control register (tbsc) timer interface b (timb) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor timer interface b (timb) 245 when tof is set and then writing a logic 0 to tof. if another timb overflow occurs before the clear ing sequence is complete, then writing logic 0 to tof has no ef fect. therefore, a tof interrupt request cannot be lost du e to inadvertent clea ring of tof. reset clears the tof bit. writing a logic 1 to tof has no effect. 1 = timb counter ha s reached modulo value. 0 = timb counter has not reached modulo value. toie ? timb overflow interrupt enable bit this read/write bit enables timb overflow interr upts when the tof bit becomes set. reset cl ears the toie bit. 1 = timb overflow interrupts enabled 0 = timb overflow interrupts disabled tstop ? timb stop bit this read/write bit stop s the timb counter. counting resumes when tstop is cleared. reset sets t he tstop bit, stopping the timb counter until software clears the tstop bit. 1 = timb counter stopped 0 = timb counter active note: do not set the tstop bit before enter ing wait mode if the timb is required to exit wait m ode. also, when the tstop bit is set and the timer is configured for input capture operation, input captures are inhibited until tstop is cleared. trst ? timb reset bit setting this write-only bit resets the timb counte r and the timb prescaler. setting trst has no ef fect on any other registers. counting resumes from $0000 . trst is cleared automatically after the timb counter is re set and always reads as logic 0. reset clears the trst bit. 1 = prescaler and timb counter cleared 0 = no effect note: setting the tstop and trst bits simultaneously stops the timb counter at a value of $0000. advance information mc68hc908mr24 ? rev. 4.1 246 timer interface b (timb) freescale semiconductor timer interface b (timb) ps[2:0] ? prescaler select bits these read/write bits select either the ptd4/atd12 pin or one of the seven prescaler outputs as the input to the timb counter as table 12-1 shows. reset clear s the ps[2:0] bits. table 12-1. pres caler selection ps[2:0] timb clock source 000 internal bus clock 1 001 internal bus clock 2 010 internal bus clock 4 011 internal bus clock 8 100 internal bus clock 16 101 internal bus clock 32 110 internal bus clock 64 111 pte0/tclkb timer interface b (timb) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor timer interface b (timb) 247 12.8.2 timb c ounter registers the two read-only timb counter regist ers contain the high and low bytes of the value in the timb counter . reading the high byte (tbcnth) latches the contents of the low byte (tbcntl) into a buffer. subsequent reads of tbcnth do not affect the latched tbcntl value until tbcntl is read. reset clears the timb counter registers. setting the timb reset bit (trst) also clears t he timb counter registers. note: if tbcnth is read during a break interrupt, be sure to unlatch tbcntl by reading tbcntl before exiting the break interrupt. otherwise, tbcntl retains the value latched during the break. register name and address: tbcnth ? $0052 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write:rrrrrrrr reset:00000000 register name and address: tbcntl ? $0053 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write:rrrrrrrr reset:00000000 r = reserved figure 12-5. timb counter registers (tbcnth and tbcntl) advance information mc68hc908mr24 ? rev. 4.1 248 timer interface b (timb) freescale semiconductor timer interface b (timb) 12.8.3 timb counter modulo registers the read/write timb modulo registers contain the modulo value for the timb counter. when the timb counter reaches the m odulo value, the overflow flag (tof) bec omes set, an d the timb counter resumes counting from $0000 at the next cl ock. writing to the high byte (tbmodh) inhibits the to f bit and overflow interr upts until the low byte (tbmodl) is written. reset sets the timb counter modulo registers. note: reset the timb counter before wr iting to the timb counter modulo registers. register name and address: tbmodh ? $0054 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:11111111 register name and address: tbmodl ? $0055 bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:11111111 figure 12-6. timb c ounter modulo registers (tbmodh and tbmodl) timer interface b (timb) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor timer interface b (timb) 249 12.8.4 timb channel stat us and control registers each of the timb channel st atus and control registers: flags input captures and output compares enables input capture and output compare interrupts selects input capture, output compare, or pwm operation selects high, low, or t oggling output on output compare selects rising edge, fall ing edge, or any edge as the active input capture trigger selects output toggl ing on timb overflow selects 100 percent pwm duty cycle selects buffered or unbuffered output compare/ pwm operation register name and address: tbsc0 ? $0056 bit 7654321bit 0 read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 register name and address: tbsc1 ? $0059 bit 7654321bit 0 read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 r reset:00000000 r= reserved figure 12-7. ti mb channel status and control regist ers (tbsc0?tbsc1) advance information mc68hc908mr24 ? rev. 4.1 250 timer interface b (timb) freescale semiconductor timer interface b (timb) chxf ? chann el x flag when channel x is an inpu t capture channel, this read/write bit is set when an active edge occurs on the channel x pin. when channel x is an output compare channel, chxf is set when the value in the timb counter registers matche s the value in the ti mb channel x registers. when chxie = 0, clear chxf by re ading timb channel x status and control register with chxf set, a nd then writing a logi c 0 to chxf. if another interrupt request occurs before the clearing sequence is complete, then writing l ogic 0 to chxf has no effect. therefore, an interrupt request cannot be lost due to inadvertent clearing of chxf. reset clears the chxf bit. writing a logic 1 to chxf has no effect. 1 = input capture or out put compare on channel x 0 = no input capture or output compare on channel x chxie ? channel x in terrupt enable bit this read/write bit enabl es timb cpu interrupts on channel x. reset clears the chxie bit. 1 = channel x cpu inte rrupt requests enabled 0 = channel x cpu interr upt requests disabled msxb ? mode select bit b this read/write bit sele cts buffered output co mpare/pwm operation. msxb exists only in the timb channel 0. setting ms0b disables the channel 1 status and control register and reverts tch1b to general-purpose i/o. reset clears the msxb bit. 1 = buffered output com pare/pwm operation enabled 0 = buffered output compar e/pwm operation disabled msxa ? mode select bit a when elsxb:a 00, this read/write bit se lects either input capture operation or unbuffered outp ut compare/pwm operation. see table 12-2 . 1 = unbuffered output compare/pwm operation 0 = input capt ure operation timer interface b (timb) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor timer interface b (timb) 251 when elsxb:a = 00, this read/write bit selects the in itial output level of the tchx pin once pwm, inpu t capture, or output compare operation is enabled. see table 12-2 . reset clears the msxa bit. 1 = initial output level low 0 = initial output level high note: before changing a channel function by writing to the msxb or msxa bit, set the tstop and trst bi ts in the timb status and control register (tbsc). elsxb and elsxa ? edge/level select bits when channel x is an i nput capture channel, th ese read/write bits control the active edge- sensing logic on channel x. when channel x is an output co mpare channel, elsxb and elsxa control the channel x output beh avior when an output compare occurs. when elsxb and elsxa are both cl ear, channel x is not connected to port e, and pin ptex /tchxb is available as a general-purpose i/o pin. however, channel x is at a state determined by these bits and becomes transparent to the respecti ve pin when pwm, input capture, or output compare mode is enabled. table 12-2 shows how elsxb and elsxa work. reset clears the elsxb and elsxa bits. note: before enabling a timb channel register for input capture operation, make sure that t he ptex/tbchx pin is stable for at least two bus clocks. tovx ? toggle-on-overflow bit when channel x is an output compar e channel, this read/write bit controls the behavior of the channel x output when the timb counter overflows. when channel x is an i nput capture channel, tovx has no effect. reset clear s the tovx bit. 1 = channel x pin toggles on timb counter overflow. 0 = channel x pin does not toggl e on timb counter overflow. advance information mc68hc908mr24 ? rev. 4.1 252 timer interface b (timb) freescale semiconductor timer interface b (timb) note: when tovx is set, a timb counter overflow takes precedence over a channel x output compare if bot h occur at the same time. chxmax ? channel x ma ximum duty cycle bit when the tovx bit is at logic 0, setting the chxmax bit forces the duty cycle of buffered and unbuffe red pwm signals to 100 percent. as figure 12-8 shows, the chxmax bit take s effect in the cycle after it is set or cleared. the output stays at the 100 percent duty cycle level until the cycle after ch xmax is cleared. table 12-2. mode, edge, and level selection msxb:msxa elsxb:elsxa mode configuration x0 00 output preset pin under port control; initialize timer output level high x1 00 pin under port control; initialize timer output level low 00 01 input capture capture on rising edge only 00 10 capture on falling edge only 00 11 capture on rising or falling edge 01 01 output compare or pwm toggle output on compare 01 10 clear output on compare 01 11 set output on compare 1x 01 buffered output compare or buffered pwm toggle output on compare 1x 10 clear output on compare 1x 11 set output on compare timer interface b (timb) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor timer interface b (timb) 253 figure 12-8. chxmax latency 12.8.5 timb c hannel registers these read/write registers contain t he captured timb c ounter value of the input capture functi on or the output compar e value of the output compare function. the stat e of the timb channel registers after reset is unknown. in input capture mode (msxb?msxa = 0:0), reading the high byte of the timb channel x registers (tbchxh) inhibits input captures until the low byte (tbchxl) is read. in output compar e mode (msxb?msxa 0:0), writing to t he high byte of the timb channel x regist ers (tbchxh) inhibits output compares until the low byte (tbchxl) is written. output overflow ptex/tchx period chxmax overflow overflow overflow overflow compare output compare output compare output compare tovx advance information mc68hc908mr24 ? rev. 4.1 254 timer interface b (timb) freescale semiconductor timer interface b (timb) register name and address: tbch0h ? $0057 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset register name and address: tbch0l ? $0058 bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: indeterminate after reset register name and address: tbch1h ? $005a bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset register name and address: tbch1l ? $005b bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: indeterminate after reset figure 12-9. timb channel registers (tbch0h/l?tbch1h/l) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor serial peripheral interface module (spi) 255 advance information ? mc68hc908mr24 section 13. serial peripheral interface module (spi) 13.1 contents 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 13.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 13.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 13.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258 13.5.1 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 13.5.2 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 13.6 transmission formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262 13.6.1 clock phase and polarity controls. . . . . . . . . . . . . . . . . . . 262 13.6.2 transmission format wh en cpha = 0 . . . . . . . . . . . . . . . 262 13.6.3 transmission format when cpha = 1 . . . . . . . . . . . . . . . 264 13.6.4 transmission initiation latency . . . . . . . . . . . . . . . . . . . . . 265 13.7 error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 13.7.1 overflow error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 13.7.2 mode fault error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 13.8 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271 13.9 resetting the spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 13.10 queuing transmissi on data . . . . . . . . . . . . . . . . . . . . . . . . . . 274 13.11 low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 13.12 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 13.12.1 miso (master in/slave out) . . . . . . . . . . . . . . . . . . . . . . . . 276 13.12.2 mosi (master out/slave in) . . . . . . . . . . . . . . . . . . . . . . . . 277 13.12.3 spsck (serial clock). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 13.12.4 ss (slave select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 13.12.5 v ss (clock ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279 13.13 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 13.13.1 spi control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 13.13.2 spi status and control register . . . . . . . . . . . . . . . . . . . . 282 13.13.3 spi data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 advance information mc68hc908mr24 ? rev. 4.1 256 serial peripheral interface module (spi) freescale semiconductor serial peripheral interface module (spi) 13.2 introduction the serial peripheral interface (s pi) module allows full-duplex, synchronous, serial communicati ons with peripheral devices. 13.3 features features of the spi module include: full-duplex operation master and slave modes double-buffered operation with separate transmit and receive registers four master mode frequencie s (maximum = bus frequency 2) maximum slave mode frequency = bus frequency serial clock with program mable polarity and phase two separately enabled interrupts with central processor unit (cpu) service: ? sprf (spi receiver full) ? spte (spi transmitter empty) mode fault error flag wi th cpu interrupt capability overflow error flag with cpu interrupt capability programmable wired-or mode i 2 c (inter-integrated ci rcuit) compatibility serial peripheral interface module (spi) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor serial peripheral interface module (spi) 257 13.4 pin name conventions the generic names of th e spi i/o pins are: ss , slave select spsck, spi serial clock mosi, master out/slave in miso, master in/slave out spi pins are shared by par allel i/o ports or have alternate functions. the full name of an spi pin re flects the name of the shared port pin or the name of an alternate pin function. the generic pin names appear in the text that follows. table 13-1 shows the full names of the spi i/o pins. table 13-1. pin name conventions generic pin names: miso mosi spsck ss full pin names: ptf3/miso ptf2/mosi ptf0/spsck ptf1/ss advance information mc68hc908mr24 ? rev. 4.1 258 serial peripheral interface module (spi) freescale semiconductor serial peripheral interface module (spi) 13.5 functional description figure 13-1 shows the structure of the spi module and figure 13-2 shows the locations and content s of the spi i/o registers. figure 13-1. spi module block diagram transmitter cpu interrupt request receiver/error cpu interrupt request 76543210 spr1 spmstr transmit data register shift register spr0 cgmout 2 clock select 2 clock divider 8 32 128 clock logic cpha cpol spi sprie spe spwom sprf spte ovrf m s pin control logic receive data register sptie spe internal bus (from sim) modfen errie control modf spmstr mosi miso spsck ss serial peripheral interface module (spi) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor serial peripheral interface module (spi) 259 the spi module allows full-duplex, synchronous, serial communication between the mcu and peripheral devices, including other mcus. software can poll the spi status flags or spi operation can be interrupt-driven. all spi interr upts can be serviced by the cpu. 13.5.1 master mode the spi operates in mast er mode when the spi ma ster bit, spmstr, is set. note: configure the spi modul es as master or sl ave before enab ling them. enable the master spi before enabling the slave spi. disable the slave spi before disabling t he master spi. see 13.13.1 spi control register . only a master spi modul e can initiate transmi ssions. software begins the transmission from a master spi module by wr iting to the spi data register. if the shift regist er is empty, the byte immediately transfers to the shift register, setti ng the spi transmitter em pty bit, spte. the byte begins shifting out on the mosi pin under the control of the serial clock. see figure 13-3 . addr. register name bit 7 6 5 4 3 2 1 bit 0 $0044 spi control register (spcr) see page 280. read: sprie r spmstr cpol cpha spwom spe sptie write: reset:00101000 $0045 spi status and control register (spscr) see page 282. read: sprf errie ovrf modf spte modfen spr1 spr0 write: r r r r reset:00001000 $0046 spi data register (spdr) see page 285. read:r7r6r5r4r3r2r1r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset r= reserved figure 13-2. spi i/o register summary advance information mc68hc908mr24 ? rev. 4.1 260 serial peripheral interface module (spi) freescale semiconductor serial peripheral interface module (spi) the spr1 and spr0 bits control t he baud rate generator and determine the speed of the sh ift register. see 13.13.2 spi status and control register . through the spsck pi n, the baud-rate generator of the master also controls the shift register of the slave peripheral. as the byte shifts out on the mosi pin of the ma ster, another byte shifts in from the slave on the master?s miso pin. the transmission ends when the receiver full bit, sprf, becomes set. at t he same time that sprf becomes set, the byte from the slave transfers to the receive data register. in normal operation, spr f signals the end of a transmission. software clears sprf by reading the sp i status and contro l register with sprf set and then r eading the spi data registe r. writing to the spi data register clears the spte bit. figure 13-3. full-duplex master-slave connections 13.5.2 slave mode the spi operates in slave mode when t he spmstr bit is clear. in slave mode the spsck pin is the input for the serial clock from the master mcu. before a data tr ansmission occurs, the ss pin of the slave spi must be at logic 0. ss must remain low unti l the transmission is complete. see 13.7.2 mode fault error . in a slave spi module, dat a enters the shift regist er under the control of the serial clock from the master spi module. after a byte enters the shift register of a slave spi, it transfers to the re ceive data regi ster, and the sprf bit is set. to prevent an over flow condition, slave software then shift register shift register baud rate generator master mcu slave mcu v dd mosi mosi miso miso spsck spsck ss ss serial peripheral interface module (spi) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor serial peripheral interface module (spi) 261 must read the receive da ta register before anothe r full byte enters the shift register. the maximum frequency of the spsck for an spi configur ed as a slave is the bus clock speed (which is twic e as fast as the fastest master spsck clock that can be generat ed). the frequency of the spsck for an spi configured as a slave does not have to correspond to any spi baud rate. the baud rate only cont rols the speed of the spsck generated by an spi configured as a master. therefore, the frequency of the spsck for an spi configured as a slave can be any frequency less than or equal to the bus speed. when the master spi starts a transm ission, the data in the slave shift register begins shifting out on the miso pin. the sl ave can load its shift register with a new byte for the next transmission by writin g to its transmit data register. the slave must write to its transmit data register at least one bus cycle before the master star ts the next transmission. otherwise, the byte already in the slave shift register shif ts out on the miso pin. data written to the slav e shift register during a transmission remains in a buffer until the end of the transmission. when the clock phase bit (cpha) is set, the first edge of spsck starts a transmission. when cpha is clear, the falling edge of ss starts a transmission. see 13.6 transmission formats . note: if the write to the data register is late, the spi transmits the data already in the shift register from the previous transmission. spsck must be in the pr oper idle state before the slave is enabled to prevent spsck from appearing as a clock edge. advance information mc68hc908mr24 ? rev. 4.1 262 serial peripheral interface module (spi) freescale semiconductor serial peripheral interface module (spi) 13.6 transmission formats during an spi transmission, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). a serial clock synchronizes shifting and sampling on the two seri al data lines. a slave select line allows selection of an i ndividual slave spi device; slave devices that are not selected do not interfere with spi bus activities. on a master spi device, the slave select line can optionally be used to indicate multiple-master bus contention. 13.6.1 clock phase and polarity controls software can select any of four co mbinations of seri al clock (spsck) phase and polarity using tw o bits in the spi cont rol register (spcr). the clock polarity is specified by the cpol control bit, which selects an active high or low clock and has no si gnificant effect on the transmission format. the clock phase (cpha) control bit se lects one of two fundamentally different transmission formats. the clock phase and polarity should be identical for the master spi device and the communicating slave device. in some cases, the phase an d polarity are changed between transmissions to allow a master devic e to communicate with peripheral slaves having diff erent requirements. note: before writing to the cp ol bit or the cpha bi t, disable the spi by clearing the spi enable bit (spe). 13.6.2 transmission format when cpha = 0 figure 13-4 shows an spi transmission in which cpha is logic 0. the figure should not be us ed as a replacement fo r data sheet parametric information.two waveforms are shown for spsck: one for cpol = 0 and another for cpol = 1. the diagram may be interpreted as a master or slave timing diagram since the serial clock ( spsck), master in/slave out (miso), and master out/slave in (m osi) pins are directly connected between the master and the slave. the miso signal is the output from the slave, and the mosi signal is the output from the master. the ss line serial peripheral interface module (spi) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor serial peripheral interface module (spi) 263 is the slave select input to the sl ave. the slave spi drives its miso output only when its slave select input (ss ) is at logic 0, so that only the selected slave drives to the master. the ss pin of the master is not shown but is assumed to be inactive. the ss pin of the master must be high or must be reconf igured as general-purpose i/o not af fecting the spi. (see 13.7.2 mode fault error .) when cpha = 0, the first spsck edge is the msb capture st robe. therefore, the sl ave must begin driving its data before the fi rst spsck edge, and a fa lling edge on the ss pin is used to start the slave dat a transmission. the slave?s ss pin must be toggled back to high and then low agai n between each byte transmitted as shown in figure 13-5 . figure 13-4. transmi ssion format (cpha = 0) figure 13-5. cpha/ss timing bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb 12345678 spsck cycle # for reference spsck, cpol = 0 spsck, cpol = 1 mosi from master miso from slave ss , to slave capture strobe byte 1 byte 3 miso/mosi byte 2 master ss slave ss cpha = 0 slave ss cpha = 1 advance information mc68hc908mr24 ? rev. 4.1 264 serial peripheral interface module (spi) freescale semiconductor serial peripheral interface module (spi) when cpha = 0 for a slave, the falling edge of ss indicates the beginning of the transmission. this causes the spi to leave its idle state and begin driving the miso pin with the msb of its data. once the transmission begins, no new data is allowed into the shift register from the transmit data register . therefore, the spi data register of the slave must be loaded with transmit dat a before the falling edge of ss . any data written after the falling edge is stor ed in the transmit data register and transferred to the shift register after the current transmission. 13.6.3 transmission format when cpha = 1 figure 13-6 shows an spi transmission in which cpha is logic 1. the figure should not be us ed as a replacement fo r data sheet parametric information. two wave forms are shown for s psck: one for cpol = 0 and another for cpol = 1. the diagram may be interpreted as a master or slave timing diagram since the serial clock ( spsck), master in/slave out (miso), and master out/slave in (m osi) pins are directly connected between the master and the slave. the miso signal is the output from the slave, and the mosi signal is the output from the master. the ss line is the slave select input to the sl ave. the slave spi drives its miso output only when its slave select input (ss ) is at logic 0, so that only the selected slave drives to the master. the ss pin of the master is not shown but is assumed to be inactive. the ss pin of the master must be high or must be reconf igured as general-purpose i/o not af fecting the spi. see 13.7.2 mode fault error . when cpha = 1, the master begins driving its mosi pin on the first spsck edge. therefore, the slave uses the first spsck edg e as a start trans mission signal. the ss pin can remain low between transmissions. thi s format may be preferable in systems having only one master and only one slave driving the miso data line. serial peripheral interface module (spi) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor serial peripheral interface module (spi) 265 figure 13-6. transmi ssion format (cpha = 1) when cpha = 1 for a slav e, the first edge of the spsck indicates the beginning of the transmission. this causes the spi to leave its idle state and begin driving the miso pin with the msb of its data. once the transmission begins, no new data is allowed into the shift register from the transmit data register . therefore, the spi data register of the slave must be loaded with transmit dat a before the first edge of spsck. any data written after the fi rst edge is stored in the transmit data register and transferred to the shift register after the current transmission. 13.6.4 transmission initiation latency when the spi is configured as a mast er (spmstr = 1), writing to the spdr starts a transmission . cpha has no ef fect on the delay to the start of the transmission, but it does affect the init ial state of the spsck signal. when cpha = 0, the spsck signal remains inactive for the first half of the first spsck cycle. when cpha = 1, the first spsck cycle begins with an edge on the spsck line from its inactive to its active level. the spi clock rate (selected by spr1:spr0) af fects the delay from the write to spdr and the start of t he spi transmission. see figure 13-7 . the internal spi clock in the mast er is a free-runni ng derivative of the internal mcu clock. to conserve power, it is enabled only when both the spe and spmstr bits are set. spsck edges occur halfway through the low time of the internal mc u clock. since the spi clock is free-running, it is uncertain where the write to the spdr occurs relative to the slower spsck. th is uncertainty causes the variation in the bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb 12345678 spsck cycle # for reference spsck, cpol = 0 spsck, cpol =1 mosi from master miso from slave ss , to slave capture strobe advance information mc68hc908mr24 ? rev. 4.1 266 serial peripheral interface module (spi) freescale semiconductor serial peripheral interface module (spi) initiation delay shown in figure 13-7 . this delay is no longer than a single spi bit time. that is, the maximum delay is two mcu bus cycles for div2, eight mcu bus cycles for div8, 32 mcu bus cycles for div32, and 128 mcu bus cycl es for div128. figure 13-7. transmissi on start delay (master) write to spdr initiation delay bus mosi spsck cpha = 1 spsck cpha = 0 spsck cycle number msb bit 6 12 clock write to spdr earliest latest spsck = internal clock 2; earliest latest 2 possible start points spsck = internal clock 8; 8 possible start points earliest latest spsck = internal clock 32; 32 possible start points earliest latest spsck = internal clock 128; 128 possible start points write to spdr write to spdr write to spdr bus clock bit 5 3 bus clock bus clock bus clock ? ? ? initiation delay from write spdr to transfer begin serial peripheral interface module (spi) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor serial peripheral interface module (spi) 267 13.7 error conditions these flags signal spi error conditions: overflow (ovrf) ? fai ling to read the spi data register before the next full byte ent ers the shift register sets the ovrf bit. the new byte does not transfer to the receive data register, and the unread byte still can be read. ovrf is in the spi status and control register. mode fault error (m odf) ? the modf bit indicates that the voltage on the slave select pin (ss ) is inconsistent with the mode of the spi. modf is in the sp i status and control register. 13.7.1 overflow error the overflow flag (ovrf) be comes set if the receiv e data register still has unread data from a previous trans mission when the capture strobe of bit 1 of the ne xt transmission occurs. if an overflow occurs, all data received after the overflow and before the ovrf bit is cleared does not transfer to the receive dat a register and does not se t the spi receiver full bit (sprf). the unread data that transferred to the receive data register before the overflow occu rred can still be read. ther efore, an overflow error always indicates the loss of data. clear the overfl ow flag by reading the spi status and cont rol register and then reading the spi data register. ovrf generates a receiv er/error cpu interrupt request if the error interrupt enable bit (erri e) is also set. modf and ovrf can generate a receiver/error cpu interrupt request. see figure 13-10 . it is not possible to enable modf or ovrf individually to generate a receiver/error cpu inte rrupt request. however, leaving modfen low prevents modf from being set. advance information mc68hc908mr24 ? rev. 4.1 268 serial peripheral interface module (spi) freescale semiconductor serial peripheral interface module (spi) if the cpu sprf interr upt is enabled and the o vrf interrupt is not, watch for an over flow condition. figure 13-8 shows how it is possible to miss an overflow. the first part of figure 13-8 shows how it is possible to read the spscr and spdr to clear t he sprf without problems. however, as illustrated by the se cond transmission example, the ovrf bit can be set in between th e time that spscr and spdr are read. figure 13-8. missed read of overflow condition in this case, an overflow can eas ily be missed. sinc e no more sprf interrupts can be generated until this ovrf is serv iced, it is not obvious that bytes are being lost as more transmissions are completed. to prevent this, either enabl e the ovrf interrupt or do another read of the spscr following the read of the spdr. this ens ures that the ovrf was not set before the sprf was clea red and that future transmissions can set the sprf bit. figure 13-9 illustrates this proc ess. generally, to avoid this second spscr read, enable the ovrf interrupt to the cpu by setting the errie bit. read read ovrf sprf byte 1 byte 2 byte 3 byte 4 byte 1 sets sprf bit. cpu reads spscr with sprf bit set cpu reads byte 1 in spdr, byte 2 sets sprf bit. cpu reads spscr with sprf bit set byte 3 sets ovrf bit. byte 3 is lost. cpu reads byte 2 in spdr, clearing sprf bit, byte 4 fails to set sprf bit because 1 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 clearing sprf bit. but not ovrf bit. ovrf bit is not cleared. byte 4 is lost. and ovrf bit clear. and ovrf bit clear. spscr spdr serial peripheral interface module (spi) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor serial peripheral interface module (spi) 269 figure 13-9. clearing sprf when ovrf interrupt is not enabled 13.7.2 mode fault error setting the spmstr bit selects master mode and configures the spsck and mosi pins as output s and the miso pin as an input. clearing spmstr selects slave mode and configur es the spsck and mosi pins as inputs and the miso pin as an output. the mode fault bit, modf, becomes set any time the st ate of the slave select pin, ss , is inconsistent with the mode selected by spmstr. to prevent spi pin contention and damage to the mcu, a mode fault error occurs if: the ss pin of a slave spi goes high during a transmission. the ss pin of a master spi goes low at any time. for the modf flag to be set, the mode fault er ror enable bit (modfen) must be set. clearing th e modfen bit does not cl ear the modf flag but does prevent modf from being se t again after modf is cleared. read read ovrf sprf byte 1 byte 2 byte 3 byte 4 1 byte 1 sets sprf bit. cpu reads spscr with sprf bit set cpu reads byte 1 in spdr, cpu reads spscr again byte 2 sets sprf bit. cpu reads spscr with sprf bit set byte 3 sets ovrf bit. byte 3 is lost. cpu reads byte 2 in spdr, cpu reads spscr again cpu reads byte 2 spdr, byte 4 sets sprf bit. cpu reads spscr. cpu reads byte 4 in spdr, cpu reads spscr again 1 2 3 clearing sprf bit. 4 to check ovrf bit. 5 6 7 8 9 clearing sprf bit. to check ovrf bit. 10 clearing ovrf bit. 11 12 13 14 2 3 4 5 6 7 8 9 10 11 12 13 14 clearing sprf bit. to check ovrf bit. spi receive complete and ovrf bit clear. and ovrf bit clear. spscr spdr advance information mc68hc908mr24 ? rev. 4.1 270 serial peripheral interface module (spi) freescale semiconductor serial peripheral interface module (spi) modf generates a receiver/error cp u interrupt request if the error interrupt enable bit (errie) is also set. t he sprf, modf, and ovrf interrupts share the same cpu in terrupt vector. mo df and ovrf can generate a receiver/error c pu interrupt request. see figure 13-10 . it is not possible to enabl e modf or ovrf indi vidually to generate a receiver/error cpu inte rrupt request. however, leaving modfen low prevents modf from being set. in a master spi with th e mode fault enable bit (m odfen) set, the mode fault flag (modf) is set if ss goes to logic 0. a m ode fault in a master spi causes these events to occur: if errie = 1, the spi generates an spi receiver/error cpu interrupt request. the spe bit is cleared. the spte bit is set. the spi state counter is cleared. the data direction regi ster of the shared i/o port regains control of port drivers. note: to prevent bus contention with another master spi after a mode fault error, clear all spi bits of the data direction regist er of the shared i/o port before enabling the spi. when configured as a slave (spmstr = 0), the modf fl ag is set if ss goes high during a trans mission. when cpha = 0, a transmission begins when ss goes low and ends once the in coming spsck goes back to its idle level following the shift of t he eighth data bit. w hen cpha = 1, the transmission begins when the sps ck leaves its idle level and ss is already low. the transmission continues until the spsck returns to its idle level following the shi ft of the last data bit. see 13.6 transmission formats . note: setting the modf flag does not clear the spmst r bit. reading spmstr when modf = 1 will indicate a mode fault er ror occurred in either master mode or slave mode. when cpha = 0, a modf occurs if a slave is selected (ss is at logic 0) and later unselected (ss is at logic 1) even if no spsck is sent to that slave. this happens because ss at logic 0 indicate s the start of the serial peripheral interface module (spi) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor serial peripheral interface module (spi) 271 transmission (miso driven out with the value of msb) for cpha = 0. when cpha = 1, a slave can be selected and then later unselected with no transmission occurri ng. therefore, modf does not occur since a transmission was never begun. in a slave spi (mstr = 0), t he modf bit generates an spi receiver/error cpu interr upt request if the errie bit is set. the modf bit does not clear th e spe bit or reset the spi in any way. software can abort the spi transmission by clear ing the spe bit of the slave. note: a logic 1 volt age on the ss pin of a slave spi puts the miso pin in a high impedance state. also, the slave spi ignores all incoming spsck clocks, even if it was already in the middle of a transmission. to clear the modf flag, read the sp scr with the modf bit set and then write to the spcr register. this ent ire clearing procedure must occur with no modf condition existing or else the flag is not cleared. 13.8 interrupts four spi status flags can be enabled to generate cpu interrupt requests as shown in table 13-2 . the spi transmitter inte rrupt enable bit (sptie ) enables the spte flag to generate transmitter cpu interrupt requests, pr ovided that the spi is enabled (spe = 1). the spi receiver interrupt enable bit (sprie) enables t he sprf bit to generate receiver cpu interrupt reques ts, provided t hat the spi is enabled (spe = 1). (see figure 13-10 .) table 13-2. spi interrupts flag request spte transmitter empty spi transmitter cpu interrupt request (sptie = 1, spe = 1) sprf receiver full spi receiver cpu interrupt request (sprie = 1) ovrf overflow spi receiver/error interrupt request (errie = 1) modf mode fault spi receiver/error interrupt request (errie = 1) advance information mc68hc908mr24 ? rev. 4.1 272 serial peripheral interface module (spi) freescale semiconductor serial peripheral interface module (spi) figure 13-10. sp i interrupt r equest generation the error interrupt enable bit (e rrie) enables both the modf and ovrf bits to generate a receiv er/error cpu in terrupt request. the mode fault enable bit (m odfen) can prevent t he modf flag from being set so that only the ovrf bit is enabled by the errie bit to generate receiver/error c pu interrupt requests. these sources in the spi status and control register can generate cpu interrupt requests: spi receiver full bit (sprf) ? the sprf bit becomes set every time a byte transfers from the sh ift register to the receive data register. if the spi receiver interr upt enable bit, sprie, is also set, sprf can generate either an sp i receiver/error cpu interrupt. spi transmitter empty (spte) ? the spte bit becomes set every time a byte transfers from the tr ansmit data regist er to the shift register. if the spi trans mit interrupt enable bit, sptie, is also set, spte can generate ei ther an spte cpu interrupt request. spte sptie sprf sprie errie modf ovrf spe spi transmitter cpu interrupt request spi receiver/error cpu interrupt request serial peripheral interface module (spi) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor serial peripheral interface module (spi) 273 13.9 resetting the spi any system reset completely resets the spi. partial resets occur whenever the spi enable bit (spe ) is low. whenever spe is low: the spte flag is set. any transmission currently in progress is aborted. the shift register is cleared. the spi state counter is cleared, making it ready for a new complete transmission. all the spi port logi c is defaulted back to being general-purpose i/o. these items are reset only by a system reset: all control bits in the spcr register all control bits in the spscr register (modfen, errie, spr1, and spr0) the status flags sprf, ovrf, and modf by not resetting the control bits when spe is low, the user can clear spe between transmissions wit hout having to set all c ontrol bits again when spe is set back high fo r the next transmission. by not resetting the spr f, ovrf, and modf flags , the user can still service these interrupts after the spi has been disabl ed. the user can disable the spi by writing 0 to the spe bit. the spi can also be disabled by a mode fault occuring in an spi th at was configured as a master with the modfen bit set. advance information mc68hc908mr24 ? rev. 4.1 274 serial peripheral interface module (spi) freescale semiconductor serial peripheral interface module (spi) 13.10 queuing transmission data the double-buffered transmit data register allows a data byte to be queued and transmitted. for an spi configured as a master, a queued data byte is transmitted immediately after the previous transmission has completed. the sp i transmitter empty flag (spte) indicates when the transmit data buffer is ready to acce pt new data. write to the transmit data register only when the spte bit is high. figure 13-11 shows the timing associated with doi ng back-to-back transmi ssions with the spi (spsck has cpha :cpol = 1:0). figure 13-11. sp rf/spte cpu interrupt timing for a slave, the transm it data buffer allows back-to-back transmissions without the slave precis ely timing its writes bet ween transmissions as in a system with a single data buffer. also, if no new data is written to the data buffer, the last value contained in the shift register is the next data word to be transmitted. bit 3 mosi spsck spte write to spdr 1 cpu writes byte 2 to spdr, queueing byte 2 cpu writes byte 1 to spdr, clearing spte bit. byte 1 transfers from transmit data 3 1 2 2 3 5 register to shift register, setting spte bit. sprf read spscr msb bit 6 bit 5 bit 4 bit 2 bit 1 lsb msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb bit 6 byte 2 transfers from transmit data cpu writes byte 3 to spdr, queueing byte byte 3 transfers from transmit data 5 8 10 8 10 4 first incoming byte transfers from shift 6 cpu reads spscr with sprf bit set. 4 6 9 second incoming byte transfers from shift 9 11 and clearing spte bit. register to shift register, setting spte bit. register to receive data register, setting sprf bit. 3 and clearing spte bit. register to shift register, setting spte bit. register to receive data register, setting sprf bit. 12 cpu reads spdr, clearing sprf bit. bit 5 bit 4 byte 1 byte 2 byte 3 7 12 read spdr 7 cpu reads spdr, clearing sprf bit. 11 cpu reads spscr with sprf bit set. cpha:cpol = 1:0 serial peripheral interface module (spi) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor serial peripheral interface module (spi) 275 for an idle master or id le slave that has no dat a loaded into its transmit buffer, the spte is set again no more than two bus cycles after the transmit buffer empties in to the shift register. th is allows the user to queue up a 16-bit value to send. for an already active slave, the load of the shift register cannot occur until the transm ission is completed. this implies that a back-to-ba ck write to the transmit data register is not possible. the spte indicates when the next write can occur. 13.11 low-power mode the wait instruction put s the mcu in a low pow er-consumption standby mode. the spi module remains active after the execution of a wait instruction. in wait mode the spi module registers are no t accessible by the cpu. any enabled cpu interrupt request from the spi module can bring the mcu out of wait mode. if spi module functions are not required during wait mode, reduce power consumption by disabl ing the spi module befor e executing the wait instruction. to exit wait mode when an overflow condition occurs, enable the ovrf bit to generate cpu interr upt requests by setti ng the error interrupt enable bit (err ie). see 13.8 interrupts . since the spte bit cannot be cleared during a break with the bcfe bit cleared, a write to the transmit data register in break mode does not initiate a transmission nor is this dat a transferred into th e shift register. therefore, a write to t he spdr in break mode with the bcfe bit cleared has no effect. advance information mc68hc908mr24 ? rev. 4.1 276 serial peripheral interface module (spi) freescale semiconductor serial peripheral interface module (spi) 13.12 i/o signals the spi module has five i/o pins and shares four of them with a parallel i/o port. the pins are: miso ? data received mosi ? data transmitted spsck ? serial clock ss ? slave select the spi has limited inte r-integrated circuit (i 2 c) capability (requiring software support) as a master in a single-master environment. to communicate with i 2 c peripherals, mosi becom es an open-drain output when the spwom bit in the spi control regi ster is set. in i 2 c communication, the mo si and miso pins are connected to a bidirectional pin from the i 2 c peripheral and through a pullup resistor to v dd . 13.12.1 miso (mas ter in/slave out) miso is one of the two spi module pins that transmits serial data. in full duplex operation, the miso pin of the mast er spi module is connected to the miso pin of the slave spi m odule. the master spi simultaneously receives data on its mi so pin and transmits dat a from its mosi pin. slave output data on the miso pin is enabl ed only when the spi is configured as a slave. the spi is configured as a slave when its spmstr bit is lo gic 0 and its ss pin is at logic 0. to support a multiple-slave system, a logic 1 on the ss pin puts the miso pin in a high-impedance state. when enabled, the spi controls dat a direction of the miso pin regardless of the state of the data direction r egister of the shared i/o port. serial peripheral interface module (spi) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor serial peripheral interface module (spi) 277 13.12.2 mosi (master out/slave in) mosi is one of the two spi module pins that trans mits serial data. in full-duplex operation, the mosi pin of the master spi module is connected to the mosi pin of the slave spi module. the master spi simultaneously transmits dat a from its mosi pin and receives data on its miso pin. when enabled, the spi controls dat a direction of the mosi pin regardless of the state of the data direction r egister of the shared i/o port. 13.12.3 spsck (serial clock) the serial clock synchronizes dat a transmission between master and slave devices. in a master mcu, the spsck pin is the cl ock output. in a slave mcu, the spsck pin is the clock input. in full-duplex operation, the master and slave mcus exchange a by te of data in eight serial clock cycles. when enabled, the spi controls dat a direction of the spsck pin regardless of the state of the data direction r egister of the shared i/o port. 13.12.4 ss (slave select) the ss pin has various func tions depending on the cu rrent state of the spi. for an spi configur ed as a slave, the ss is used to select a slave. for cpha = 0, the ss is used to define the st art of a transmission. see 13.6 transmission formats . since it is used to i ndicate the start of a transmission, the ss must be toggled high and low between each byte transmitted for the cpha = 0 format . however, it can remain low between transmissions for the cpha = 1 format. see figure 13-12 . advance information mc68hc908mr24 ? rev. 4.1 278 serial peripheral interface module (spi) freescale semiconductor serial peripheral interface module (spi) figure 13-12. cpha/ss timing when an spi is configur ed as a slave, the ss pin is always configured as an input. it cannot be used as a general-purpose i/o regardless of the state of the modfen control bit. however, the modfen bit can still prevent the state of the ss from creating a modf error. see 13.13.2 spi status and control register . note: a logic 1 voltage on the ss pin of a slave spi put s the miso pin in a high-impedance state. the slave spi ignores all incoming spsck clocks, even if it was already in the middle of a transmission. when an spi is configur ed as a master, the ss input can be used in conjunction with the modf flag to prevent multip le masters from driving mosi and spsck. (see 13.7.2 mode fault error .) for the state of the ss pin to set the modf flag, the modfen bit in the spsck register must be set. if the modfen bit is low for an spi master, the ss pin can be used as a general-purpo se i/o under the control of the data direction register of the shared i/o port. with modfen high, it is an input-only pin to the spi regardle ss of the state of the data direction regi ster of the shared i/o port. the cpu can always read the state of the ss pin by configuring the appropriate pin as an input an d reading the port data register. see table 13-3 . byte 1 byte 3 miso/mosi byte 2 master ss slave ss cpha = 0 slave ss cpha = 1 serial peripheral interface module (spi) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor serial peripheral interface module (spi) 279 13.12.5 v ss (clock ground) v ss is the ground return for the seri al clock pin, sps ck, and the ground for the port output buffer s. to reduce t he ground return path loop and minimize radio frequency (rf) emissions, connect the ground pin of the slave to the v ss pin of the master. 13.13 i/o registers three registers control and monitor spi operation: spi control register, spcr spi status and control register, spscr spi data register, spdr 13.13.1 spi control register the spi control r egister (spcr): enables spi modul e interrupt requests selects cpu interrupt reques ts or dma service requests configures the spi modul e as master or slave selects serial clock polarity and phase configures the spsck, mosi, and miso pins as open-drain outputs enables the spi module table 13-3. spi configuration spe spmstr modfen spi conf iguration state of ss logic 0 x (1) 1. x = don?t care x not enabled general-purpose i/o; ss ignored by spi 1 0 x slave input-only to spi 11 0 master without modf general-purpose i/o; ss ignored by spi 1 1 1 master with modf input-only to spi advance information mc68hc908mr24 ? rev. 4.1 280 serial peripheral interface module (spi) freescale semiconductor serial peripheral interface module (spi) sprie ? spi receiver interrupt enable bit this read/write bi t enables cpu interrupt re quests generated by the sprf bit. the sprf bit is set when a byte transfers from the shift register to the receive data r egister. reset clear s the sprie bit. 1 = sprf cpu interr upt requests enabled 0 = sprf cpu interr upt requests disabled spmstr ? spi master bit this read/write bit sele cts master mode oper ation or slave mode operation. reset sets the spmstr bit. 1 = master mode 0 = slave mode cpol ? clock polarity bit this read/write bit det ermines the logic st ate of the spsck pin between transmissions. see figure 13-4 and figure 13-6 . to transmit data between spi modules, the spi modules must have identical cpol values. reset clears the cpol bit. cpha ? clock phase bit this read/write bit contro ls the timing relationship between the serial clock and spi data. see figure 13-4 and figure 13-6 . to transmit data between spi modules , the spi modules must have identical cpha bits. when cpha = 0, the ss pin of the slave spi module must be set to logic 1 between bytes. see figure 13-12 . reset sets the cpha bit. address: $0044 bit 7654321bit 0 read: sprie r spmstr cpol cpha spwom spe sptie write: reset:00101000 r= reserved figure 13-13. spi cont rol register (spcr) serial peripheral interface module (spi) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor serial peripheral interface module (spi) 281 when cpha = 0 for a slave, the falling edge of ss indicates the beginning of the transmissi on. this causes the sp i to leave its idle state and begin driving the miso pin with the msb of its data, once the transmission begins, no new data is allowed into the shift register from the data regi ster. therefore, the slave data register must be loaded with the desired transmit data before the fall ing edge of ss . any data written after the falling edge is stored in the data register and transferred to the shift register at the current transmission. when cpha = 1 for a slav e, the first edge of t he spsck indicates the beginning of the tr ansmission. the same applies when ss is high for a slave. the miso pin is held in a high-impedance state, and the incoming spsck is ignored. in cert ain cases, it may also cause the modf flag to be set. see 13.7.2 mode fault error . a logic 1 on the ss pin does not in any way affect the state of the spi state machine. spwom ? spi wired-or mode bit this read/write bit disa bles the pullup devices on pins spsck, mosi, and miso so that those pins become open-drain outputs. 1 = wired-or spsck, mosi, and miso pins 0 = normal push-pull sp sck, mosi, and miso pins spe ? spi enable bit this read/write bi t enables the spi module. clearing spe causes a partial reset of the spi. see 13.9 resetting the spi . reset clears the spe bit. 1 = spi module enabled 0 = spi module disabled sptie? spi transmit interrupt enable bit this read/write bi t enables cpu interrupt re quests generated by the spte bit. spte is set when a byte transfers fr om the transmit data register to the shif t register. reset cl ears the sptie bit. 1 = spte cpu interr upt requests enabled 0 = spte cpu interr upt requests disabled advance information mc68hc908mr24 ? rev. 4.1 282 serial peripheral interface module (spi) freescale semiconductor serial peripheral interface module (spi) 13.13.2 spi status and control register the spi status and control register (spscr) contains flags to signal these conditions: receive data register full failure to clear sprf bit before next byte is received (overflow error) inconsistent logic level on ss pin (mode fault error) transmit data r egister empty the spi status and control r egister also contains bi ts that perform these functions: enable error interrupts enable mode fault error detection select master spi baud rate sprf ? spi receiver full bit this clearable, read-only flag is set each time a byte transfers from the shift register to the receive data register. sprf generates a cpu interrupt request if the s prie bit in the spi contro l register is set also. during an sprf cpu interrupt (dma s = 0), the cpu cl ears sprf by reading the spi st atus and control regist er with sprf set and then reading the spi data register. reset clears the sprf bit. 1 = receive data register full 0 = receive data register not full address: $0045 bit 7654321bit 0 read: sprf errie ovrf modf spte modfen spr1 spr0 write:r rrr reset:00001000 r=reserved figure 13-14. spi status an d control register (spscr) serial peripheral interface module (spi) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor serial peripheral interface module (spi) 283 errie ? error interrupt enable bit this read/write bit enabl es the modf and ovrf bits to generate cpu interrupt requests. re set clears t he errie bit. 1 = modf and ovrf can generat e cpu interrupt requests. 0 = modf and ovrf cannot gener ate cpu interrupt requests. ovrf ? overflow bit this clearable, read- only flag is set if software does not read the byte in the receive data register before the next full byte enters the shift register. in an overflow condition, th e byte already in the receive data register is unaffected, and t he byte that shifted in last is lost. clear the ovrf bit by reading the spi status and control register with ovrf set and then reading the receive data regi ster. reset clears the ovrf bit. 1 = overflow 0 = no overflow modf ? mode fault bit this clearable, read-only flag is set in a slave spi if the ss pin goes high during a transmission with the modfen bit set. in a master spi, the modf flag is set if the ss pin goes low at any time with the modfen bit set. clear the modf bi t by reading the spi status and control register (sp scr) with modf set and t hen writing to the spi control register (spcr). reset clears the modf bit. 1 = ss pin at inappropriate logic level 0 = ss pin at appropria te logic level spte ? spi transmi tter empty bit this clearable, read-only flag is set each time t he transmit data register transfers a by te into the shift regi ster. spte generates an spte cpu interrupt request or an spte dma service request if the sptie bit in the spi contro l register is set also. note: do not write to the spi data r egister unless the spte bit is high. advance information mc68hc908mr24 ? rev. 4.1 284 serial peripheral interface module (spi) freescale semiconductor serial peripheral interface module (spi) for an idle master of idle slave that has no data loaded into its transmit buffer, the spte will be set again within two bus cycles since the transmit buffer empties into the shift register . this allows the user to queue up a 16-bi t value to send. for an already active slave, the load of the shift register cannot occur until the transmision is completed. this implies that a back- to-back write to the transmit data register is not possible. the spte indicates when the next write can occur. reset sets the spte bit. 1 = transmit data register empty 0 = transmit data r egister not empty modfen ? mode fault enable bit this read/write bit, when set to 1, allows the modf flag to be set. if the modf flag is set, clearing the modfen does not clear the modf flag. if the spi is enabled as a master and the modfen bit is low, then the ss pin is available as a general-purpose i/o. if the modfen bit is set, then th is pin is not available as a general-purpose i/o. when the spi is enabled as a slave, the ss pin is not available as a general-purpose i/o regardl ess of the value of modfen. see 13.12.4 ss (slave select) . if the modfen bit is lo w, the level of the ss pin does not affect the operation of an enabled spi config ured as a master. for an enabled spi configured as a slave, havin g modfen low only prevents the modf flag from being se t. it does not affect any other part of spi operation. see 13.7.2 mode fault error . spr1 and spr0 ? spi baud rate select bits in master mode, these read/write bits select one of four baud rates as shown in table 13-4 . spr1 and spr0 have no effect in slave mode. reset clears spr1 and spr0. serial peripheral interface module (spi) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor serial peripheral interface module (spi) 285 use this formula to calc ulate the spi baud rate: where: cgmout = base clock output of the clock generator module (cgm) bd = baud rate divisor 13.13.3 spi data register the spi data register consists of t he read-only receive data register and the write-only transmit data register . writing to the spi data register writes data into the transmit data r egister. reading the spi data register reads data from the rece ive data register. the tr ansmit data and receive data registers are separat e registers that can c ontain different values. see figure 13-1 . r7:r0/t7:t0 ? receive/ transmit data bits note: do not use read-modi fy-write instructions on t he spi data register since the register read is not the same as th e register written. table 13-4. spi master baud rate selection spr1:spr0 baud rate divisor (bd) 00 2 01 8 10 32 11 128 baud rate cgmout 2bd -------------- ------------ = address: $0046 bit 7654321bit 0 read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: indeterminate after reset figure 13-15. spi data register (spdr) advance information mc68hc908mr24 ? rev. 4.1 286 serial peripheral interface module (spi) freescale semiconductor serial peripheral interface module (spi) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor serial communications interface module (sci) 287 advance information ? mc68hc908mr24 section 14. serial communica tions interface module (sci) 14.1 contents 14.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 14.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 14.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289 14.4.1 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 14.4.2 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 14.4.2.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 14.4.2.2 character transmission . . . . . . . . . . . . . . . . . . . . . . . . . 293 14.4.2.3 break characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 14.4.2.4 idle characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 14.4.2.5 inversion of transm itted output. . . . . . . . . . . . . . . . . . . 295 14.4.2.6 transmitter in terrupts. . . . . . . . . . . . . . . . . . . . . . . . . . .295 14.4.3 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 14.4.3.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 14.4.3.2 character reception . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 14.4.3.3 data sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 14.4.3.4 framing errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 14.4.3.5 receiver wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 14.4.3.6 receiver interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 14.4.3.7 error interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 14.5 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 14.6 sci during break module interrupts. . . . . . . . . . . . . . . . . . . .302 14.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 14.7.1 pte2/txd (transmit data). . . . . . . . . . . . . . . . . . . . . . . . . 303 14.7.2 pte1/rxd (receive data ) . . . . . . . . . . . . . . . . . . . . . . . . . 303 14.8 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 14.8.1 sci control regi ster 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 14.8.2 sci control regi ster 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 advance information mc68hc908mr24 ? rev. 4.1 288 serial communications interface module (sci) freescale semiconductor serial communications interface module (sci) 14.8.3 sci control regi ster 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 14.8.4 sci status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 14.8.5 sci status register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 14.8.6 sci data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 14.8.7 sci baud rate register . . . . . . . . . . . . . . . . . . . . . . . . . . 317 14.2 introduction this section describes the serial co mmunications interf ace module (sci, version d), which allows high- speed asynchronous communications with peripheral devic es and other mcus. 14.3 features features of the sci module include: full-duplex operation standard mark/space non-re turn-to-zero (nrz) format 32 programmable baud rates programmable 8-bit or 9-bit character length separately enabled trans mitter and receiver separate receiver and transmi tter cpu interrupt requests separate receiver and transmitter programmable transm itter output polarity two receiver wakeup methods: ? idle line wakeup ? address mark wakeup serial communications interface module (sci) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor serial communications interface module (sci) 289 interrupt-driven operation with eight interrupt flags: ? transmitter empty ? transmission complete ? receiver full ? idle receiver input ? receiver overrun ? noise error ? framing error ? parity error receiver framin g error detection hardware parity checking 1/16 bit-time noise detection 14.4 functional description figure 14-1 shows the structure of th e sci module. the sci allows full-duplex, asynchronous, nrz seri al communication among the mcu and remote devices, including other mcus. the transmitter and receiver of the sci operate indepe ndently, although they us e the same baud rate generator. during normal oper ation, the cpu monitors the status of the sci, writes the data to be transmi tted, and processes received data. advance information mc68hc908mr24 ? rev. 4.1 290 serial communications interface module (sci) freescale semiconductor serial communications interface module (sci) figure 14-1. sci m odule block diagram scte tc scrf idle or nf fe pe sctie tcie scrie ilie te re rwu sbk r8 t8 orie feie peie bkf rpf sci data receive shift register sci data register transmit shift register neie m wake ilty flag control transmit control receive control data selection control wakeup pty pen register transmitter interrupt control receiver interrupt control error interrupt control control ensci loops ensci pte1/rxd pte2/txd internal bus txinv loops 4 16 pre- scaler baud rate generator f op addr. register name bit 7 6 5 4 3 2 1 bit 0 $0038 sci control register 1 (scc1) see page 304. read: loops ensci txinv m wake ilty pen pty write: reset:00000000 figure 14-2. sci i/o register summary serial communications interface module (sci) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor serial communications interface module (sci) 291 14.4.1 data format the sci uses the standard non-return-to-zero mark /space data format illustrated in figure 14-3 . figure 14-3. sci data formats $0039 sci control register 2 (scc2) see page 307. read: sctie tcie scrie ilie te re rwu sbk write: reset:00000000 $003a sci control register 3 (scc3) see page 310. read: r8 t8 00 orie neie feie peie write: r r r reset:uu000000 $003b sci status register 1 (scs1) see page 312. read: scte tc scrf idle or nf fe pe write:rrrrrrrr reset:11000000 $003c sci status register 2 (scs2) see page 316. read: 0 0 0 0 0 0 bkf rpf write:rrrrrrrr reset:00000000 $003d sci data register (scdr) see page 317. read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset $003e sci baud rate register (scbr) see page 317. read: 0 0 scp1 scp0 0 scr2 scr1 scr0 write: r r r reset:00000000 r = reserved u = unaffected addr. register name bit 7 6 5 4 3 2 1 bit 0 figure 14-2. sci i/o regi ster summary (continued) bit 5 start bit bit 0 bit 1 next stop bit start bit 8-bit data format bit m in scc1 clear start bit bit 0 next stop bit start bit 9-bit data format bit m in scc1 set bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 2 bit 3 bit 4 bit 6 bit 7 possible parity bit possible parity bit advance information mc68hc908mr24 ? rev. 4.1 292 serial communications interface module (sci) freescale semiconductor serial communications interface module (sci) 14.4.2 transmitter figure 14-4 shows the structure of the sci transmitter. figure 14-4. sci transmitter 14.4.2.1 character length the transmitter can accommod ate either 8-bit or 9- bit data. the state of the m bit in sci control register 1 (scc1) deter mines character length. when transmitting 9-bit data, bit t8 in sci control register 3 (scc3) is the ninth bi t (bit 8). pen pty h876543210l 11-bit transmit stop start t8 scte sctie tcie sbk tc f op parity generation msb sci data register load from scdr shift enable preamble all 1s break all 0s transmitter control logic shift register tc sctie tcie scte transmitter cpu interrupt request m ensci loops te pte2/txd txinv internal bus 4 pre- scaler scp1 scp0 scr2 scr1 scr0 baud divider 16 serial communications interface module (sci) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor serial communications interface module (sci) 293 14.4.2.2 character transmission during an sci transmission, the transmit shift regist er shifts a character out to the pte2/txd pin. the sci dat a register (scdr) is the write-only buffer between the internal data bus and the transmi t shift register. to initiate an sci transmission: 1. enable the sci by writing a logi c 1 to the enable sci bit (ensci) in sci control r egister 1 (scc1). 2. enable the transmitter by writi ng a logic 1 to the transmitter enable bit (te) in sci cont rol register 2 (scc2). 3. clear the sci transmit ter empty bit by first reading sci status register 1 (scs1) and t hen writing to the scdr. 4. repeat step 3 for each subsequent transmission. at the start of a transmission, tran smitter control logic automatically loads the transmit shift register with a preamble of logic 1s. after the preamble shifts out, control logic tr ansfers the scdr data into the transmit shift register. a logic 0 start bit automati cally goes into the least significant bit (lsb) position of the transmit shift regist er. a logic 1 stop bit goes into the most signi ficant bit (msb) position. the sci transmitter empt y bit, scte, in scs1 becomes set when the scdr transfers a byte to the trans mit shift register. the scte bit indicates that the scdr c an accept new data from the internal data bus. if the sci transmit interrupt enable bit, sctie, in scc2 is also set, the scte bit generates a transmi tter cpu interrupt request. when the transmit shift register is not transmitting a character, the pte2/txd pin goes to the idle condition, logic 1. if at any time software clears the ensci bit in sci control register 1 (s cc1), the transmitter and receiver relinquish contro l of the port f pins. 14.4.2.3 break characters writing a logic 1 to the send break bit, sbk, in scc2 loads the transmit shift register with a break character. a break character contains all logic 0s and has no start, stop, or parity bit. break character length depends on the m bit in scc1. as long as sbk is at logi c 1, transmitter logic advance information mc68hc908mr24 ? rev. 4.1 294 serial communications interface module (sci) freescale semiconductor serial communications interface module (sci) continuously loads break characters in to the transmit shif t register. after software clears the sbk bit, the shif t register finishes transmitting the last break character and then tr ansmits at least one logic 1. the automatic logic 1 at the end of a break character guarantees the recognition of the start bit of the nex t character. the sci recognizes a break characte r when a start bit is followed by eight or nine logic 0 data bits and a logic 0 where the stop bit should be. receiving a break character has these effects on sci registers: sets the framing erro r bit (fe) in scs1 sets the sci receiver full bit (scrf) in scs1 clears the sci dat a register (scdr) clears the r8 bit in scc3 sets the break flag bit (bkf) in scs2 may set the overrun (or), noise flag (nf), parity error (pe), or reception-in-progr ess flag (rpf) bits 14.4.2.4 idle characters an idle character contains all logic 1s and has no st art, stop, or parity bit. idle character length depends on the m bit in scc1. th e preamble is a synchronizing idle character that begins every transmission. if the te bit is cleared during a tr ansmission, the pte2/txd pin becomes idle after completion of the transmission in pr ogress. clearing and then setting the te bit duri ng a transmission queues an id le character to be sent after the character currently being transmitted. note: when queueing an idle character, return the te bit to logic 1 before the stop bit of the current ch aracter shifts out to th e pte2/txd pin. setting te after the stop bi t appears on pte2/txd c auses data previously written to the scdr to be lost. a good time to toggle the te bit is when the scte bit becomes set and just before writing the next byte to the scdr. serial communications interface module (sci) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor serial communications interface module (sci) 295 14.4.2.5 inversion of transmitted output the transmit inversion bit (txinv) in sci control r egister 1 (scc1) reverses the polarity of transmitted da ta. all transmitted values, including idle, break, start, and stop bits, are inverted when txinv is at logic 1. see 14.8.1 sci control register 1 . 14.4.2.6 transmitter interrupts these conditions can ge nerate cpu interrupt requests from the sci transmitter: sci transmitter empty (scte) ? the scte bit in scs1 indicates that the scdr has transferred a character to the transmit shift register. scte can gene rate a transmitter cp u interrupt request. setting the sci transmit interrupt enable bit, sctie, in scc2 enables the scte bit to generat e transmitter cpu interrupt requests. transmission complete (tc) ? the tc bit in scs1 indicates that the transmit shift register and the scdr are em pty and that no break or idle character has been generated. th e transmission complete interrupt enable bit, tcie , in scc2 enables the tc bit to generate transmitter cpu interrupt requests. 14.4.3 receiver figure 14-5 shows the structure of the sci receiver. 14.4.3.1 character length the receiver can accommodat e either 8-bit or 9-bi t data. the state of the m bit in sci control register 1 (scc1) determines character length. when receiving 9-bit data, bit r8 in sci control register 2 (scc2) is the ninth bit (bit 8). when rece iving 8-bit data, bit r8 is a copy of the eighth bit (bit 7). advance information mc68hc908mr24 ? rev. 4.1 296 serial communications interface module (sci) freescale semiconductor serial communications interface module (sci) figure 14-5. sci receiver block diagram all 1s all 0s m wake ilty pen pty bkf rpf h876543210l 11-bit receive shift register stop start data recovery or orie nf neie fe feie pe peie scrie scrf ilie idle wakeup logic parity checking msb error cpu interrupt request cpu interrupt request sci data register r8 orie neie feie peie scrie ilie rwu scrf idle or nf fe pe pte1/rx internal bus pre- scaler baud divider 4 16 scp1 scp0 scr2 scr1 scr0 f op serial communications interface module (sci) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor serial communications interface module (sci) 297 14.4.3.2 character reception during an sci re ception, the receive shift regi ster shifts characters in from the pte1/rxd pin. the sci data register (scdr) is the read-only buffer between the inter nal data bus and the re ceive shift register. after a complete character shifts into the receive shift register, the data portion of the character transfers to the scdr. the sci receiver full bit, scrf, in sci status regi ster 1 (scs1) becomes se t, indicating that the received byte can be read. if the sci receive interrupt enable bit, scrie, in scc2 is also set, the scrf bi t generates a receiver cpu interrupt request. 14.4.3.3 data sampling the receiver samples the pte1/rxd pin at the rt clock rate. the rt clock is an internal signal with a frequency 16 times the baud rate. to adjust for baud rate mismatch, the rt clock is resynchronized at these times (see figure 14-6 ): after every start bit after the receiver detects a data bit change from l ogic 1 to logic 0 (after the majority of data bit samples at rt8, rt9, and rt10 return a valid logic 1 and the majo rity of the next rt8, rt9, and rt10 samples return a valid logic 0) to locate the start bit, data recovery logic does an asyn chronous search for a logic 0 preceded by three logic 1s. when the falling edge of a possible start bit occurs, the rt clock begins to count to 16. to verify the start bit and to detect noise, data recovery logic takes samples at rt3, rt5, and rt7. table 14-1 summarizes t he results of the start bit verification samples. advance information mc68hc908mr24 ? rev. 4.1 298 serial communications interface module (sci) freescale semiconductor serial communications interface module (sci) figure 14-6. receiver data sampling if start bit verification is not successf ul, the rt clock is reset and a new search for a start bit begins. to determine the value of a data bit and to detect noise, recovery logic takes samples at r t8, rt9, and rt10. table 14-2 summarizes the results of the data bit samples. rt clock reset rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt5 rt8 rt7 rt6 rt11 rt10 rt9 rt15 rt14 rt13 rt12 rt16 rt1 rt2 rt3 rt4 start bit qualification start bit verification data sampling samples rt clock rt clock state start bit lsb pte1/rxd table 14-1. start bit verification rt3, rt5, and rt7 samples start bit verification noise flag 000 yes 0 001 yes 1 010 yes 1 011 no 0 100 yes 1 101 no 0 110 no 0 111 no 0 serial communications interface module (sci) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor serial communications interface module (sci) 299 note: the rt8, rt9, and rt10 samp les do not affect star t bit verification. if any or all of the rt8, rt9, and rt10 start bit samples are logic 1s following a successful start bit verifica tion, the noise flag (nf) is set and the receiver assumes that the bit is a start bit. to verify a stop bit and to detect noise, recovery logic takes samples at rt8, rt9, and rt10. table 14-3 summarizes the resu lts of the stop bit samples. table 14-2. data bit recovery rt8, rt9, and rt10 samples data bit determination noise flag 000 0 0 001 0 1 010 0 1 011 1 1 100 0 1 101 1 1 110 1 1 111 1 0 table 14-3. stop bit recovery rt8, rt9, and rt10 samples framing error flag noise flag 000 1 0 001 1 1 010 1 1 011 0 1 100 1 1 101 0 1 110 0 1 111 0 0 advance information mc68hc908mr24 ? rev. 4.1 300 serial communications interface module (sci) freescale semiconductor serial communications interface module (sci) 14.4.3.4 framing errors if the data recovery l ogic does not detect a logi c 1 where the stop bit should be in an in coming character, it sets t he framing error bit, fe, in scs1. the fe flag is set at the same time that the scrf bit is set. a break character that has no stop bit also sets the fe bit. 14.4.3.5 receiver wakeup so that the mcu can ignore tr ansmissions intended only for other receivers in multiple-receiver system s, the receiver can be put into a standby state. setting the receiver wa keup bit, rwu, in scc2 puts the receiver into a standby state during which re ceiver interrupts are disabled. depending on the state of the wake bit in scc1, either of two conditions on the pte1/rxd pin can bring the receiv er out of the standby state: address mark ? an address mark is a logic 1 in the most significant bit position of a rece ived character. when the wake bit is set, an address mark wakes t he receiver from the standby state by clearing the rwu bit. the addr ess mark also sets the sci receiver full bit, scrf. software can then compare the character containing the address mark to the user-defined address of the receiver. if they ar e the same, the receiv er remains awake and processes the characters that fo llow. if they are not the same, software can set the rwu bit and put the rece iver back into the standby state. idle input line condition ? when the wake bit is clear, an idle character on the pte1/rxd pin wakes the receiver from the standby state by clearing the rw u bit. the idle character that wakes the receiver does not set the receiver idle bit, idle, or the sci receiver full bit, scrf. the id le line type bit, ilty, determines whether the receiver begins counting logic 1s as idle character bits after the start bit or after the stop bit. note: clearing the wake bit after the pte1/rxd pi n has been idle can cause the receiver to wa ke up immediately. serial communications interface module (sci) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor serial communications interface module (sci) 301 14.4.3.6 receiver interrupts these sources can generate cpu in terrupt requests from the sci receiver: sci receiver full ( scrf) ? the scrf bit in scs1 indicates that the receive shift register has tran sferred a characte r to the scdr. scrf can generate a receiver cp u interrupt request. setting the sci receive interrupt enable bit, s crie, in scc2 enables the scrf bit to generate rece iver cpu interrupts. idle input (idle) ? the idle bit in scs1 i ndicates that 10 or 11 consecutive logic 1s shifted in from the pte1/rxd pin. the idle line interrupt enable bi t, ilie, in scc2 enables the idle bit to generate cpu inte rrupt requests. 14.4.3.7 error interrupts these receiver error flags in scs1 can generate cpu in terrupt requests: receiver overrun (or) ? the or bit indicates that the receive shift register shifted in a new character before the previous character was read from the scdr. the previous character remains in the scdr, and the new character is lost. the overrun interrupt enable bit, orie, in scc3 enables or to generate sci error cpu interrupt requests. noise flag (nf) ? the nf bit is set when the sci detects noise on incoming data or break characters, including start, data, and stop bits. the noise error interrupt enabl e bit, neie, in scc3 enables nf to generate sci erro r cpu interrupt requests. framing error (fe) ? the fe bit in scs1 is se t when a logic 0 occurs where the receiver expec ts a stop bit. the framing error interrupt enable bit, feie, in scc3 enables fe to generate sci error cpu interrupt requests. parity error (pe) ? the pe bit in scs1 is set when the sci detects a parity error in incoming data. the parity error interrupt enable bit, peie, in scc3 enables pe to gener ate sci error cpu interrupt requests. advance information mc68hc908mr24 ? rev. 4.1 302 serial communications interface module (sci) freescale semiconductor serial communications interface module (sci) 14.5 wait mode the wait and stop in structions put the mcu in low power- consumption standby modes. the sci module remains active af ter the execution of a wait instruction. in wait m ode the sci module register s are not accessible by the cpu. any enabled c pu interrupt request fr om the sci module can bring the mcu out of wait mode. if sci module functions are not requ ired during wait mode, reduce power consumption by disabling the m odule before executing the wait instruction. 14.6 sci during br eak module interrupts the system integration module (sim) c ontrols whether status bits in other modules can be cleared during interrupts generated by the break module. the bcfe bit in the sim break flag control register (sbfcr) enables software to cl ear status bits durin g the break state. to allow software to clear status bi ts during a break interrupt, write a logic 1 to the bcfe bit. if a status bi t is cleared during t he break state, it remains cleared when the m cu exits the break state. to protect status bits du ring the break state, writ e a logic 0 to the bcfe bit. with bcfe at logic 0 (its defaul t state), software can read and write i/o registers during the break state wi thout affecting status bits. some status bits have a 2-st ep read/write clearing proced ure. if software does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is at logic 0. after the break, doing the second step clears the status bit. serial communications interface module (sci) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor serial communications interface module (sci) 303 14.7 i/o signals port f shares two of its pins with the sci module. the two sci input/output (i/o) pins are: pte2/txd ? transmit data pte1/rxd ? receive data 14.7.1 pte2/txd (transmit data) the pte2/txd pin is the serial data output from the sci transmitter. the sci shares the pte2/txd pin with port f. when the sci is enabled, the pte2/txd pin is an output regardle ss of the state of the ddrf5 bit in data direction register f (ddrf). 14.7.2 pte1/rxd (receive data) the pte1/rxd pin is the serial data input to the sci receiver. the sci shares the pte1/rxd pin with por t f. when the sc i is enabled, the pte1/rxd pin is an input regardless of the state of the ddrf4 bit in data direction register f (ddrf). 14.8 i/o registers these i/o registers control and monitor sci operation: sci control register 1, scc1 sci control register 2, scc2 sci control register 3, scc3 sci status register 1, scs1 sci status register 2, scs2 sci data register, scdr sci baud rate register, scbr advance information mc68hc908mr24 ? rev. 4.1 304 serial communications interface module (sci) freescale semiconductor serial communications interface module (sci) 14.8.1 sci cont rol register 1 sci control regi ster 1 (scc1): enables loop-mode operation enables the sci controls output polarity controls character length controls sci wakeup method controls idle character detection enables parity function controls parity type loops ? loop mode select bit this read/write bit enabl es loop mode operatio n. in loop mode the pte6/rxd pin is disconnected from the sci, and the transmitter output goes into the rece iver input. both t he transmitter and the receiver must be enabled to use loop mode. reset clears the loops bit. 1 = loop mode enabled 0 = normal operation enabled ensci ? enable sci bit this read/write bit enabl es the sci and the sc i baud rate generator. clearing ensci sets the scte and tc bits in sc i status register 1 and disables transmitter interrupt s. reset clears the ensci bit. 1 = sci enabled 0 = sci disabled address: $0038 bit 7654321bit 0 read: loops ensci txinv m wake ilty pen pty write: reset:00000000 figure 14-7. sci cont rol register 1 (scc1) serial communications interface module (sci) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor serial communications interface module (sci) 305 txinv ? transmit inversion bit this read/write bit reverses the polarity of transmitted data. reset clears the txinv bit. 1 = transmitter output inverted 0 = transmitter out put not inverted note: setting the txinv bit inve rts all transmitted values , including idle, break, start, and stop bits. m ? mode (character length) bit this read/write bit deter mines whether sci characters are eight or nine bits long. see table 14-4 . the ninth bit can serve as an extra stop bit, as a receiver wakeup signal, or as a parity bit. reset clears the m bit. 1 = 9-bit sci characters 0 = 8-bit sci characters wake ? wakeup condition bit this read/write bit deter mines which condition wakes up the sci: a logic 1 (address mark) in the most significant bit (m sb) position of a received character or an idle cond ition on the pte6/rxd pin. reset clears the wake bit. 1 = address mark wakeup 0 = idle line wakeup ilty ? idle line type bit this read/write bit deter mines when the sci star ts counting logic 1s as idle character bits. the counting begins either after the start bit or after the stop bit. if the count begins after the start bit, then a string of logic 1s preceding the stop bit may cause false recognition of an idle character. beginning the count after the stop bit avoids false idle character recognition, but re quires properly synchronized transmissions. reset clears the ilty bit. 1 = idle character bit c ount begins afte r stop bit. 0 = idle character bit c ount begins afte r start bit. advance information mc68hc908mr24 ? rev. 4.1 306 serial communications interface module (sci) freescale semiconductor serial communications interface module (sci) pen ? parity enable bit this read/write bit enables the sci parit y function. see table 14-4 . when enabled, the parity function in serts a parity bit in the most significant bit position. see figure 14-3 . reset clears the pen bit. 1 = parity function enabled 0 = parity function disabled pty ? parity bit this read/write bit determines w hether the sci generates and checks for odd parity or ev en parity. see table 14-4 . reset clears the pty bit. 1 = odd parity 0 = even parity note: changing the pty bit in the middle of a transmission or reception can generate a parity error. table 14-4. character format selection control bits character format mpen:pty start bits data bits parity stop bits character length 0 0x 1 8 none 1 10 bits 1 0x 1 9 none 1 11 bits 010 17even1 10 bits 0 11 1 7 odd 1 10 bits 110 18even1 11 bits 1 11 1 8 odd 1 11 bits serial communications interface module (sci) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor serial communications interface module (sci) 307 14.8.2 sci cont rol register 2 sci control regi ster 2 (scc2): enables these cpu interrupt requests: ? enables the scte bit to gener ate transmitter cpu interrupt requests ? enables the tc bi t to generate transmi tter cpu interrupt requests ? enables the scrf bit to gener ate receiver cpu interrupt requests ? enables the idle bit to gene rate receiver cpu interrupt requests enables the transmitter enables the receiver enables sci wakeup transmits sci break characters sctie ? sci transmit interrupt enable bit this read/write bi t enables the scte bit to generate sci transmitter cpu interrupt requests. se tting the sctie bit in scc3 enables scte cpu interrupt requests. re set clears t he sctie bit. 1 = scte enabled to gener ate cpu interrupt 0 = scte not enabled to generate cpu interrupt address: $0039 bit 7654321bit 0 read: sctie tcie scrie ilie te re rwu sbk write: reset:00000000 figure 14-8. sci cont rol register 2 (scc2) advance information mc68hc908mr24 ? rev. 4.1 308 serial communications interface module (sci) freescale semiconductor serial communications interface module (sci) tcie ? transmission comple te interrupt enable bit this read/write bit enable s the tc bit to generat e sci transmitter cpu interrupt requests. reset clears the tcie bit. 1 = tc enabled to generate cpu interrupt requests 0 = tc not enabled to generate cpu interrupt requests scrie ? sci receive interrupt enable bit this read/write bi t enables the scrf bit to generate sci receiver cpu interrupt requests. setting the scrie bit in scc3 enables the scrf bit to generate cpu interrupt requests. reset clears the scrie bit. 1 = scrf enabled to gener ate cpu interrupt 0 = scrf not enabled to generate cpu interrupt ilie ? idle line interrupt enable bit this read/write bit enables the idle bit to gener ate sci receiver cpu interrupt requests. rese t clears the ilie bit. 1 = idle enabled to generate cpu interrupt requests 0 = idle not enabl ed to generate cp u interrupt requests te ? transmitt er enable bit setting this read/write bit begin s the transmission by sending a preamble of 10 or 11 logi c 1s from the transmit shift register to the pte2/txd pin. if software clears t he te bit, the transmitter completes any transmission in progress before th e pte2/txd returns to the idle condition (logic 1). clearing and then setting te during a transmission queues an idle character to be sent after the character currently being transmitted. reset clears the te bit. 1 = transmitt er enabled 0 = transmitt er disabled note: writing to the te bit is not allowed when the enab le sci bit (ensci) is clear. ensci is in sci control register 1. serial communications interface module (sci) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor serial communications interface module (sci) 309 re ? receiver enable bit setting this read/write bit enables the receiver. clearing the re bit disables the receiver but does not a ffect receiver interrupt flag bits. reset clears the re bit. 1 = receiver enabled 0 = receiver disabled note: writing to the re bit is not allowed w hen the enable sci bit (ensci) is clear. ensci is in sci control register 1. rwu ? receiver wakeup bit this read/write bit puts the receiver in a st andby state during which receiver interrupt s are disabled. the wake bit in scc1 determines whether an idle input or an address mark brings the receiver out of the standby state and clear s the rwu bit. rese t clears the rwu bit. 1 = standby state 0 = normal operation sbk ? send break bit setting and then clearing this r ead/write bit transmits a break character followed by a logic 1. the logic 1 after the break character guarantees recognition of a valid start bit. if sbk remains set, the transmitter continuously transmits break characters with no logic 1s between them. reset clears the sbk bit. 1 = transmit break characters 0 = no break charac ters being transmitted note: do not toggle the sbk bi t immediately after se tting the scte bit. toggling sbk too early causes the sci to send a break character instead of a preamble. advance information mc68hc908mr24 ? rev. 4.1 310 serial communications interface module (sci) freescale semiconductor serial communications interface module (sci) 14.8.3 sci cont rol register 3 sci control regi ster 3 (scc3): stores the ninth sci data bit rece ived and the ninth sci data bit to be transmitted enables sci receiver full (scrf) enables sci transmi tter empty (scte) enables the foll owing interrupts: ? receiver overrun interrupts ? noise error interrupts ? framing error interrupts ? parity error interrupts r8 ? received bit 8 when the sci is receiving 9-bit char acters, r8 is the read-only ninth bit (bit 8) of the received characte r. r8 is received at the same time that the scdr receives the other eight bits. when the sci is receiving 8-bit charac ters, r8 is a copy of the eighth bit (bit 7). reset has no effect on the r8 bit. t8 ? transmitted bit 8 when the sci is transmi tting 9-bit characters , t8 is the read/write ninth bit (bit 8) of the transmitted character. t8 is loaded into the transmit shift register at the same time that the scdr is loaded into the transmit shift register. re set has no effect on the t8 bit. address: $003a bit 7654321bit 0 read: r8 t8 00 orie neie feie peie write: r r r reset:uu000000 r = reserved u = unaffected figure 14-9. sci cont rol register 3 (scc3) serial communications interface module (sci) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor serial communications interface module (sci) 311 orie ? receiver overr un interrupt enable bit this read/write bit enabl es sci error cpu interrupt requests generated by the receiver overrun bit, or. 1 = sci error cpu interrupt r equests from or bit enabled 0 = sci error cpu interrupt r equests from or bit disabled neie ? receiver noise error interrupt enable bit this read/write bit enabl es sci error cpu interrupt requests generated by the noise error bi t, ne. reset clears neie. 1 = sci error cpu interrupt r equests from ne bit enabled 0 = sci error cpu interrupt r equests from ne bit disabled feie ? receiver framing error interrupt enable bit this read/write bit enabl es sci error cpu interrupt requests generated by the framing error bit, fe. reset clears feie. 1 = sci error cpu interrupt requests from fe bit enabled 0 = sci error cpu interrupt r equests from fe bit disabled peie ? receiver parity error interrupt enable bit this read/write bit enables sci receiver cpu interrupt requests generated by the par ity error bit, pe. see 14.8.4 sci status register 1 . reset clears peie. 1 = sci error cpu interrupt r equests from pe bit enabled 0 = sci error cpu interrupt r equests from pe bit disabled advance information mc68hc908mr24 ? rev. 4.1 312 serial communications interface module (sci) freescale semiconductor serial communications interface module (sci) 14.8.4 sci status register 1 sci status register 1 (s cs1) contains flags to signal these conditions: transfer of scdr data to trans mit shift register complete transmission complete transfer of receive shift r egister data to scdr complete receiver input idle receiver overrun noisy data framing error parity error scte ? sci transmi tter empty bit this clearable, read-only bit is set when the scdr transfers a character to the transmit shift register. scte can generate an sci transmitter cpu interrupt request. when the sctie bit in scc2 is set, scte generates an sci transmitter cpu interrupt r equest. in normal operation, clear the sct e bit by reading sc s1 with scte set and then writing to scdr. re set sets the scte bit. 1 = scdr data transferred to transmit shift register 0 = scdr data not transferred to transmit shift register address: $003b bit 7654321bit 0 read: scte tc scrf idle or nf fe pe write:rrrrrrrr reset:11000000 r = reserved figure 14-10. sci status register 1 (scs1) serial communications interface module (sci) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor serial communications interface module (sci) 313 tc ? transmission complete bit this read-only bit is set when the sc te bit is set, and no data, preamble, or break character is being transmitted. tc generates an sci transmitter cpu interrupt request if the tcie bit in scc2 is also set. tc is cleared automatically when data, preamble, or break is queued and ready to be sent. there may be up to 1.5 transmitter clocks of latency between queuei ng data, preambl e, and break and the transmission actually star ting. reset sets the tc bit. 1 = no transmission in progress 0 = transmission in progress scrf ? sci receiver full bit this clearable, read-only bit is set when the data in the receive shift register transfers to the sci data register. scrf c an generate an sci receiver cpu interrupt request. w hen the scrie bit in scc2 is set, scrf generates a cpu inte rrupt request. in norm al operation, clear the scrf bit by readi ng scs1 with scrf set and then reading the scdr. reset clears scrf. 1 = received data available in scdr 0 = data not available in scdr idle ? receiver idle bit this clearable, read-only bit is set when 10 or 11 consecutive logic 1s appear on the receiver input. idle generates an sci error cpu interrupt request if the ilie bit in s cc2 is also set. clear the idle bit by reading scs1 with idle set a nd then reading the scdr. after the receiver is enabled, it must receive a valid c haracter that sets the scrf bit before an idle condition can set the idle bit. also, after the idle bit has been cleared, a valid character must again set the scrf bit before an idle condition can se t the idle bit. reset clears the idle bit. 1 = receiver input idle 0 = receiver input active or id le since the idle bit was cleared advance information mc68hc908mr24 ? rev. 4.1 314 serial communications interface module (sci) freescale semiconductor serial communications interface module (sci) or ? receiver overrun bit this clearable, read-only bit is se t when software fails to read the scdr before the receive shift regist er receives the next character. the or bit generates an sci error cpu interrupt request if the orie bit in scc3 is also set. the data in the shift regist er is lost, but the data already in the scdr is not affected. clear the or bit by reading scs1 with or set and then reading the scdr. rese t clears the or bit. 1 = receive shift register full and scrf = 1 0 = no receiver overrun software latency may allow an over run to occur between reads of scs1 and scdr in the fl ag-clearing sequence. figure 14-11 shows the normal flag- clearing sequence and an example of an overrun caused by a delayed flag-clearin g sequence. the delayed read of scdr does not clear t he or bit because or was not set when scs1 was read. byte 2 caused the overrun and is lost. the next flag-clearing sequence reads byte 3 in the scdr inst ead of byte 2. in applications that are subject to software la tency or in which it is important to know which byte is lost due to an overrun, the flag-clearing routine can check the or bit in a second read of scs1 after reading the data register. nf ? receiver noise flag bit this clearable, read-only bit is set when the sci detects noise on the pte1/rxd pin. nf generates an nf cpu interrupt request if the neie bit in scc3 is also se t. clear the nf bit by reading scs1 and then reading the scdr. rese t clears the nf bit. 1 = noise detected 0 = no noise detected fe ? receiver framing error bit this clearable, read-only bit is set when a logic 0 is accepted as the stop bit. fe generates an sci error cpu interrupt request if the feie bit in scc3 also is set. clear the fe bit by reading scs1 with fe set and then reading the scdr. reset clears the fe bit. 1 = framing error detected 0 = no framing error detected serial communications interface module (sci) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor serial communications interface module (sci) 315 pe ? receiver parity error bit this clearable, read-only bit is set when the sci detects a parity error in incoming data. pe generates a pe cpu interrupt request if the peie bit in scc3 is al so set. clear the pe bit by reading scs1 with pe set and then readi ng the scdr. reset clears the pe bit. 1 = parity error detected 0 = no parity error detected figure 14-11. fl ag clearing sequence byte 1 normal flag clearing sequence read scs1 scrf = 1 read scdr byte 1 scrf = 1 scrf = 1 byte 2 byte 3 byte 4 or = 0 read scs1 scrf = 1 or = 0 read scdr byte 2 scrf = 0 read scs1 scrf = 1 or = 0 scrf = 1 scrf = 0 read scdr byte 3 scrf = 0 byte 1 read scs1 scrf = 1 read scdr byte 1 scrf = 1 scrf = 1 byte 2 byte 3 byte 4 or = 0 read scs1 scrf = 1 or = 1 read scdr byte 3 delayed flag clearing sequence or = 1 scrf = 1 or = 1 scrf = 0 or = 1 scrf = 0 or = 0 advance information mc68hc908mr24 ? rev. 4.1 316 serial communications interface module (sci) freescale semiconductor serial communications interface module (sci) 14.8.5 sci status register 2 sci status register 2 (s cs2) contains flags to signal these conditions: break character detected incoming data bkf ? break flag this clearable, read-only bit is set when the sci detects a break character on the pte1/rxd pin. in scs1, the fe and scrf bits are also set. in 9-bit ch aracter transmissions, t he r8 bit in scc3 is cleared. bkf does not generate a c pu interrupt request. clear bkf by reading scs2 with bkf set and then reading th e scdr. once cleared, bkf can become set again only after logic 1s again appear on the pte1/rxd pin followed by another break character. reset clears the bkf bit. 1 = break character detected 0 = no break ch aracter detected rpf ?reception-in-progress flag this read-only bit is set when the receiver detec ts a logic 0 during the rt1 time period of t he start bit search. rp f does not generate an interrupt request. rpf is reset after the receiver detects false start bits (usually from noise or a baud rate mismatch, or when the receiver detects an idle character. pol ling rpf before disabling the sci module or entering stop mode can show whether a reception is in progress. 1 = reception in progress 0 = no reception in progress address: $003c bit 7654321bit 0 read: 000000bkfrpf write:rrrrrrrr reset:00000000 r= reserved figure 14-12. sci status register 2 (scs2) serial communications interface module (sci) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor serial communications interface module (sci) 317 14.8.6 sci data register the sci data register (scdr) is the buffer between the internal data bus and the receive and transmit shift r egisters. reset has no effect on data in the sci data register. r7/t7:r0/t0 ? receive/transmit data bits reading address $003d accesses th e read-only received data bits, r7:r0. writing to addr ess $003d writes the da ta to be transmitted, t7:t0. reset has no effect on the sci data register. 14.8.7 sci baud rate register the baud rate register (scbr) selects the baud rate for bo th the receiver and the transmitter. address: $003d bit 7654321bit 0 read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset figure 14-13. sci data register (scdr) address: $003e bit 7654321bit 0 read: 0 0 scp1 scp0 0 scr2 scr1 scr0 write: r r r reset:00000000 r = reserved figure 14-14. sci baud rate register (scbr) advance information mc68hc908mr24 ? rev. 4.1 318 serial communications interface module (sci) freescale semiconductor serial communications interface module (sci) scp1 and scp0 ? sci baud rate prescaler bits these read/write bits select the baud rate prescaler divisor as shown in table 14-5 . reset clears scp1 and scp0. scr2?scr0 ? sci baud rate select bits these read/write bits select the sc i baud rate divisor as shown in table 14-6 . reset clears scr2?scr0. use this formula to calc ulate the sci baud rate: where: f op = internal operating frequency pd = prescaler divisor bd = baud rate divisor table 14-7 shows the sci baud rates that can be generated with a 4.9152-mhz crystal with the cg m set for an f op of 7.3728 mhz and the cgm set for an f op of 4.9152 mhz. table 14-5. sci baud rate prescaling scp1:scp0 prescaler divisor (pd) 00 1 01 3 10 4 11 13 table 14-6. sci baud rate selection scr2:scr1:scr0 baud rate divisor (bd) 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 baud rate f op 64 pd bd --------------------- --------------- = serial communications interface module (sci) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor serial communications interface module (sci) 319 . table 14-7. sci baud ra te selection examples scp1:scp0 prescaler divisor (pd) scr2:scr1:scr0 baud rate divisor (bd) baud rate (f op = 7.3728 mhz) baud rate (f op = 4.9152 mhz) 00 1 000 1 115,200 76,800 00 1 001 2 57,600 38,400 00 1 010 4 28,800 19,200 00 1 011 8 14,400 9600 00 1 100 16 7200 4800 00 1 101 32 3600 2400 00 1 110 64 1800 1200 00 1 111 128 900 600 01 3 000 1 38,400 25,600 01 3 001 2 19,200 12,800 01 3 010 4 9600 6400 01 3 011 8 4800 3200 01 3 100 16 2400 1600 01 3 101 32 1200 800 01 3 110 64 600 400 01 3 111 128 300 200 10 4 000 1 28,800 19,200 10 4 001 2 14,400 9600 10 4 010 4 7200 4800 10 4 011 8 3600 2400 10 4 100 16 1800 1200 10 4 101 32 900 600 10 4 110 64 450 300 10 4 111 128 225 150 11 13 000 1 8861.5 5907.7 11 13 001 2 4430.7 2953.8 11 13 010 4 2215.4 1476.9 11 13 011 8 1107.7 738.5 11 13 100 16 553.8 369.2 11 13 101 32 276.9 184.6 11 13 110 64 138.5 92.3 11 13 111 128 69.2 46.2 advance information mc68hc908mr24 ? rev. 4.1 320 serial communications interface module (sci) freescale semiconductor serial communications interface module (sci) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor input/output (i/o) ports 321 advance information ? mc68hc908mr24 section 15. input/output (i/o) ports 15.1 contents 15.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 15.3 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 15.3.1 port a data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 15.3.2 data direction register a . . . . . . . . . . . . . . . . . . . . . . . . . 324 15.4 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 15.4.1 port b data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 15.4.2 data direction register b. . . . . . . . . . . . . . . . . . . . . . . . . . 326 15.5 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 15.5.1 port c data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 15.5.2 data direction register c . . . . . . . . . . . . . . . . . . . . . . . . . 328 15.6 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 15.7 port e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 15.7.1 port e data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 15.7.2 data direction register e . . . . . . . . . . . . . . . . . . . . . . . . . 332 15.8 port f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 15.8.1 port f data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 15.8.2 data direction register f . . . . . . . . . . . . . . . . . . . . . . . . . 334 advance information mc68hc908mr24 ? rev. 4.1 322 input/output (i/o) ports freescale semiconductor input/output (i/o) ports 15.2 introduction thirty-seven bidirectional input-output (i/o) pins and seven input pins form six parallel ports. all i/o pins are programmable as inputs or outputs. when using the 56-pin package version of the mc68hc908mr24: set the data direction register bi ts in ddrc such that bit 1 is written to a logic 1 (a long with any other output bits on port c). set the data direction register bits in ddre such that bits 0, 1, and 2 are written to a logic 1 (along with any other output bits on port e). set the data direction register bits in ddrf such that bits 0, 1, 2, and 3 are written to a logic 1 (along with any other output bits on port f). note: connect any unused i/o pins to an appr opriate logic level, either v dd or v ss . although pwm6?pwm1 do not r equire termination for proper operation, termination reduces e xcess current consumption and the possibility of el ectrostatic damage. addr. register name bit 7 6 5 4 3 2 1 bit 0 $0000 port a data register (pta) see page 324. read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset $0001 port b data register (ptb) see page 326. read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset $0002 port c data register (ptc) see page 328. read: 0 ptc6 ptc5 ptc4 ptc3 ptc2 ptc1 ptc0 write: r reset: unaffected by reset r= reserved figure 15-1. i/o port register summary input/output (i/o) ports mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor input/output (i/o) ports 323 $0003 port d data register (ptd) see page 330. read: 0 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write:rrrrrrrr reset: unaffected by reset $0004 data direction register a (ddra) see page 324. read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 $0005 data direction register b (ddrb) see page 326. read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 $0006 data direction register c (ddrc) see page 328. read: 0 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: r reset:00000000 $0008 port e data register (pte) see page 331. read: pte7 pte6 pte5 pte4 pte3 pte2 pte1 pte0 write: reset: unaffected by reset $0009 port f data register (ptf) see page 333. read: 0 0 ptf5 ptf4 ptf3 ptf2 ptf1 ptf0 write: r r reset: unaffected by reset $000a unimplemented $000b unimplemented $000c data direction register e (ddre) see page 332. read: ddre7 ddre6 ddre5 ddre4 ddre3 ddre2 ddre1 ddre0 write: reset:00000000 $000d data direction register f (ddrf) see page 334. read: 0 0 ddrf5 ddrf4 ddrf3 ddrf2 ddrf1 ddrf0 write: r r reset: 000000 addr. register name bit 7 6 5 4 3 2 1 bit 0 r= reserved figure 15-1. i/o port re gister summary (continued) advance information mc68hc908mr24 ? rev. 4.1 324 input/output (i/o) ports freescale semiconductor input/output (i/o) ports 15.3 port a port a is an 8-bit, general-pur pose, bidirectional i/o port. 15.3.1 port a data register the port a data register (p ta) contains a data latch for each of the eight port a pins. pta[7:0] ? port a data bits these read/write bits are software programmable. data direction of each port a pin is under the control of the corresponding bit in data direction register a. reset has no effect on port a data. 15.3.2 data dir ection register a data direction register a (ddra) dete rmines whether each port a pin is an input or an output. wr iting a logic 1 to a d dra bit enables the output buffer for the corresponding port a pi n; a logic 0 dis ables the output buffer. address: $0000 bit 7654321bit 0 read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset figure 15-2. port a data register (pta) address: $0004 bit 7654321bit 0 read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 figure 15-3. data direct ion register a (ddra) input/output (i/o) ports mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor input/output (i/o) ports 325 ddra[7:0] ? data dire ction register a bits these read/write bits control port a data direction. reset clears ddra[7:0], configuring all port a pins as inputs. 1 = corresponding port a pin configured as output 0 = corresponding port a pin configured as input note: avoid glitches on port a pi ns by writing to the port a data register before changing data direction regist er a bits fr om 0 to 1. figure 15-4 shows the port a i/o logic. figure 15-4. port a i/o circuit when bit ddrax is a l ogic 1, reading address $0000 reads the ptax data latch. when bit ddrax is a logic 0, reading address $0000 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 15-1 summarizes the operation of the port a pins. table 15-1. port a pin functions ddra bit pta bit i/o pin mode accesses to ddra accesses to pta read/write read write 0 x (1) 1. x = don?t care input, hi-z (2) 2. hi-z = high impedance ddra[7:0] pin pta[7:0] (3) 3. writing affects data register, but does not affect input. 1 x output ddra[7:0] pta[7:0] pta[7:0] read ddra ($0004) write ddra ($0004) reset write pta ($0000) read pta ($0000) ptax ddrax ptax internal data bus advance information mc68hc908mr24 ? rev. 4.1 326 input/output (i/o) ports freescale semiconductor input/output (i/o) ports 15.4 port b port b is an 8-bit, general-purpose, bi directional i/o port that shares its pins with the analog-to-digi tal convertor (adc) module. 15.4.1 port b data register the port b data register (p tb) contains a data latch for each of the eight port b pins. ptb[7:0] ? port b data bits these read/write bits are software-p rogrammable. data direction of each port b pin is under the control of the corresponding bit in data direction register b. reset has no effect on port b data. 15.4.2 data dir ection register b data direction register b (ddrb) dete rmines whether each port b pin is an input or an output. wr iting a logic 1 to a d drb bit enables the output buffer for the corresponding port b pi n; a logic 0 dis ables the output buffer. address: $0001 bit 7654321bit 0 read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset figure 15-5. port b data register (ptb) address: $0005 bit 7654321bit 0 read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 figure 15-6. data direct ion register b (ddrb) input/output (i/o) ports mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor input/output (i/o) ports 327 ddrb[7:0] ? data dire ction register b bits these read/write bits control port b data direction. reset clears ddrb[7:0], configuring all port b pins as inputs. 1 = corresponding port b pin configured as output 0 = corresponding port b pin configured as input note: avoid glitches on port b pi ns by writing to the port b data register before changing data direction regist er b bits fr om 0 to 1. figure 15-7 shows the port b i/o logic. figure 15-7. port b i/o circuit when bit ddrbx is a l ogic 1, reading address $0001 reads the ptbx data latch. when bit ddrbx is a logic 0, reading address $0001 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 15-2 summarizes the operation of the port b pins. table 15-2. port b pin functions ddrb bit ptb bit i/o pin mode accesses to ddrb accesses to ptb read/write read write 0 x (1) 1. x = don?t care input, hi-z (2) 2. hi-z = high impedance ddrb[7:0] pin ptb[7:0] (3) 3. writing affects data register, but does not affect input. 1 x output ddrb[7:0] ptb[7:0] ptb[7:0] read ddrb ($0005) write ddrb ($0005) reset write ptb ($0001) read ptb ($0001) ptbx ddrbx ptbx internal data bus advance information mc68hc908mr24 ? rev. 4.1 328 input/output (i/o) ports freescale semiconductor input/output (i/o) ports 15.5 port c port c is a 7-bit, general -purpose, bidirectional i/ o port that shares two of its pins with th e analog-to-digital c onvertor module (adc). 15.5.1 port c data register the port c data register (ptc) contains a data latch for each of the seven port c pins. ptc[6:0] ? port c data bits these read/write bits are software-p rogrammable. data direction of each port c pin is under the control of the corresponding bit in data direction register c. reset has no effect on port c data. 15.5.2 data dir ection register c data direction register c (ddrc) determines whet her each port c pin is an input or an output. writ ing a logic 1 to a dd rc bit enables the output buffer for the corresponding port c pi n; a logic 0 dis ables the output buffer. address: $0002 bit 7654321bit 0 read: 0 ptc6 ptc5 ptc4 ptc3 ptc2 ptc1 ptc0 write: r reset: unaffected by reset r = reserved figure 15-8. port c data register (ptc) address: $0006 bit 7654321bit 0 read: 0 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: r reset:00000000 r= reserved figure 15-9. data direct ion register c (ddrc) input/output (i/o) ports mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor input/output (i/o) ports 329 ddrc[6:0] ? data dire ction register c bits these read/write bits control port c data direction. reset clears ddrc[6:0], configuring all port c pins as inputs. 1 = corresponding port c pin configured as output 0 = corresponding port c pin configured as input note: avoid glitches on port c pins by writ ing to the port c dat a register before changing data direction regist er c bits fr om 0 to 1. figure 15-10 shows the port c i/o logic. figure 15-10. port c i/o circuit when bit ddrcx is a l ogic 1, reading address $0002 reads the ptcx data latch. when bit ddrcx is a logic 0, reading address $0002 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 15-3 summarizes the operation of the port c pins. table 15-3. port c pin functions ddrc bit ptc bit i/o pin mode accesses to ddrc accesses to ptc read/write read write 0 x (1) 1. x = don?t care input, hi-z (2) 2. hi-z = high impedance ddrc[6:0] pin ptc[6:0] (3) 3. writing affects data register, but does not affect input. 1 x output ddrc[6:0] ptc[6:0] ptc[6:0] read ddrc ($0006) write ddrc ($0006) reset write ptc ($0002) read ptc ($0002) ptcx ddrcx ptcx internal data bus advance information mc68hc908mr24 ? rev. 4.1 330 input/output (i/o) ports freescale semiconductor input/output (i/o) ports 15.6 port d port d is a 7-bit, input- only port that shares its pi ns with the pulse width modulator for motor control module (pmc). the port d data register (ptd) contains a data latch for each of the seven port pins. ptd[6:0] ? port d data bits these read/write bits are software programmable. reset has no effect on port d data. figure 15-12 shows the port d input logic. figure 15-12. port d input circuit reading address $0003 reads the voltage level on the pin. table 15-1 summarizes the operation of the port d pins. address: $0003 bit 7654321bit 0 read: 0 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write:rrrrrrrr reset: unaffected by reset r = reserved figure 15-11. port d da ta register (ptd) table 15-4. port d pin functions ptd bit pin mode accesses to ptd read write x (1) 1. x = don?t care input, hi-z (2) 2. hi-z = high impedance pin ptd[6:0] (3) 3. writing affects data regist er, but does not affect input. read ptd ($0003) ptdx internal data bus input/output (i/o) ports mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor input/output (i/o) ports 331 15.7 port e port e is an 8-bit, special function port that shares five of its pins with the timer interface module (tim) and tw o of its pins with the serial communications interf ace module (sci). 15.7.1 port e data register the port e data register (p te) contains a data latch for each of the eight port e pins. pte[7:0] ? port e data bits pte[7:0] are read/write, software- programmable bits. data direction of each port e pin is under the control of the co rresponding bit in data direction register e. note: data direction register e (ddre) does not affect the data direction of port e pins that are being used by the tima or timb. however, the ddre bits always determine whether reading port e returns the states of the latches or the states of the pins. address: $0008 bit 7654321bit 0 read: pte7 pte6 pte5 pte4 pte3 pte2 pte1 pte0 write: reset: unaffected by reset figure 15-13. port e da ta register (pte) advance information mc68hc908mr24 ? rev. 4.1 332 input/output (i/o) ports freescale semiconductor input/output (i/o) ports 15.7.2 data dir ection register e data direction register e (ddre) dete rmines whether each port e pin is an input or an output. wr iting a logic 1 to a d dre bit enables the output buffer for the corresponding port e pi n; a logic 0 dis ables the output buffer. ddre[7:0] ? data dire ction register e bits these read/write bits control port e data direction. reset clears ddre[7:0], configuring all port e pins as inputs. 1 = corresponding port e pin configured as output 0 = corresponding port e pin configured as input note: avoid glitches on port e pi ns by writing to the port e data register before changing data direction regist er e bits fr om 0 to 1. figure 15-15 shows the port e i/o logic. figure 15-15. port e i/o circuit address: $000c bit 7654321bit 0 read: ddre7 ddre6 ddre5 ddre4 ddre3 ddre2 ddre1 ddre0 write: reset:00000000 figure 15-14. data direct ion register e (ddre) read ddre ($000c) write ddre ($000c) reset write pte ($0008) read pte ($0008) ptex ddrex ptex internal data bus input/output (i/o) ports mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor input/output (i/o) ports 333 when bit ddrex is a l ogic 1, reading address $0008 reads the ptex data latch. when bit ddrex is a logic 0, reading address $0008 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 15-5 summarizes the operation of the port e pins. 15.8 port f port f is a 6-bit, specia l function port that shares four of its pins with the serial peripheral interface module (s pi) and two pins with the serial communications interface (sci). 15.8.1 port f data register the port f data register (p tf) contains a data latc h for each of the six port f pins. table 15-5. port e pin functions ddre bit pte bit i/o pin mode accesses to ddre accesses to pte read/write read write 0 x (1) 1. x = don?t care input, hi-z (2) 2. hi-z = high impedance ddre[7:0] pin pte[7:0] (3) 3. writing affects data register, but does not affect input. 1 x output ddre[7:0] pte[7:0] pte[7:0] address: $0009 bit 7654321bit 0 read: 0 0 ptf5 ptf4 ptf3 ptf2 ptf1 ptf0 write: r r reset: unaffected by reset r = reserved figure 15-16. port f data register (ptf) advance information mc68hc908mr24 ? rev. 4.1 334 input/output (i/o) ports freescale semiconductor input/output (i/o) ports ptf[5:0] ? port f data bits these read/write bits are software programmable. data direction of each port f pin is under the control of the correspondi ng bit in data direction register f. rese t has no effect on ptf[5:0]. note: data direction register f (ddrf) does not affect th e data direction of port f pins that are being used by the spi or sci module. however, the ddrf bits always determine whether reading port f retu rns the states of the latches or the states of the pins. 15.8.2 data dir ection register f data direction register f (ddrf) det ermines whether each port f pin is an input or an output. writing a logic 1 to a ddrf bit enables the output buffer for the corresponding port f pi n; a logic 0 dis ables the output buffer. ddrf[5:0] ? data direction register f bits these read/write bits control port f data direction. reset clears ddrf[5:0], configuring a ll port f pins as inputs. 1 = corresponding port f pi n configured as output 0 = corresponding port f pi n configured as input note: avoid glitches on port f pins by writ ing to the port f dat a register before changing data direction regist er f bits from 0 to 1. figure 15-18 shows the port f i/o logic. address: $000d bit 7654321bit 0 read: 0 0 ddrf5 ddrf4 ddrf3 ddrf2 ddrf1 ddrf0 write: r r read: 000000 r = reserved figure 15-17. data dir ection register f (ddrf) input/output (i/o) ports mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor input/output (i/o) ports 335 figure 15-18. port f i/o circuit when bit ddrfx is a l ogic 1, reading address $0009 reads the ptfx data latch. when bit dd rfx is a logic 0, r eading address $0009 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 15-6 summarizes the operation of the port f pins. table 15-6. port f pin functions ddrf bit ptf bit i/o pin mode accesses to ddrf accesses to ptf read/write read write 0 x (1) 1. x = don?t care input, hi-z (2) 2. hi-z = high impedance ddrf[6:0] pin ptf[6:0] (3) 3. writing affects data register, but does not affect input. 1 x output ddrf[6:0] ptf[6:0] ptf[6:0] read ddrf ($000d) write ddrf ($000d) reset write ptf ($0009) read ptf ($0009) ptfx ddrfx ptfx internal data bus advance information mc68hc908mr24 ? rev. 4.1 336 input/output (i/o) ports freescale semiconductor input/output (i/o) ports mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor computer operating properly (cop) 337 advance information ? mc68hc908mr24 section 16. computer operating properly (cop) 16.1 contents 16.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 16.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .338 16.4 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 16.4.1 cgmxclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .339 16.4.2 copctl write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .339 16.4.3 power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 16.4.4 internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340 16.4.5 reset vector fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340 16.4.6 copd (cop disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340 16.5 cop control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340 16.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .341 16.7 monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .341 16.8 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 16.2 introduction this section describes the comput er operating properly module, a free-running counter that generates a reset if allowed to overflow. the cop module helps softwa re recover from runaway code. prevent a cop reset by periodically cl earing the cop counter. advance information mc68hc908mr24 ? rev. 4.1 338 computer operating properly (cop) freescale semiconductor computer operating properly (cop) 16.3 functional description figure 16-1 shows the structure of the cop module. figure 16-1. cop block diagram addr. register name bit 7654321bit 0 $ffff cop control register (copctl) see page 340. read: low byte of reset vector write: clear cop counter reset: unaffected by reset figure 16-2. cop i/o register summary copctl write cgmxclk reset vector fetch sim reset circuit sim reset status register internal reset sources (1) sim clear bits 12?4 13-bit sim counter clear all bits 6-bit cop counter copd (from config) reset copctl write clear cop module cop counter no te 1. see 7.4.2 active resets from internal sources . computer operating properly (cop) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor computer operating properly (cop) 339 the cop counter is a free-running, 6- bit counter precede d by the 13-bit system integration module (sim) counter. if not cl eared by software, the cop counter overflows and generates an asynchronous reset after 2 18 ?2 4 cgmxclk cycles. with a 4.9152 -mhz crystal, the cop timeout period is 53.3 ms. writing any value to location $ffff before overflow occurs clears the cop c ounter and prevents reset. a cop reset pulls the rst pin low for 32 cgm xclk cycles and sets the cop bit in the sim reset st atus register (srsr). see 7.7.2 sim reset status register . note: place cop clearing instructions in the main program and not in an interrupt subroutine. su ch an interrupt subrout ine could keep the cop from generating a reset even while the main pr ogram is not working properly. 16.4 i/o signals this section describes the signals shown in figure 16-1 . 16.4.1 cgmxclk cgmxclk is the crystal oscillator output si gnal. cgmxclk frequency is equal to the crystal frequency. 16.4.2 copctl write writing any value to the cop c ontrol register (copctl) (see 16.5 cop control register ) clears the cop counter a nd clears bits 12 through 4 of the sim counter. readi ng the cop control register returns the reset vector. 16.4.3 power-on reset the power-on reset (por) ci rcuit in the sim clears the sim counter 4096 cgmxclk cycles after power-up. advance information mc68hc908mr24 ? rev. 4.1 340 computer operating properly (cop) freescale semiconductor computer operating properly (cop) 16.4.4 internal reset an internal reset clears the sim counter and the cop counter. 16.4.5 reset vector fetch a reset vector fetch occurs when the vector addres s appears on the data bus. a reset vector fetch clears the sim counter. 16.4.6 copd (cop disable) the copd signal reflec ts the state of the cop di sable bit (copd) in the configuration regist er (config). (see section 5. configuration register (config) .) 16.5 cop control register the cop control register is locat ed at address $ffff and overlaps the reset vector. writing any value to $ffff clears t he cop counter and starts a new timeout per iod. reading location $ffff returns the low byte of the reset vector. address: $ffff bit 7654321bit 0 read: low byte of reset vector write: clear cop counter reset: unaffected by reset figure 16-3. cop cont rol register (copctl) computer operating properly (cop) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor computer operating properly (cop) 341 16.6 interrupts the cop does not generate cpu interrupt requests. 16.7 monitor mode the cop is disabled in monitor mode when v hi is present on the irq pin or on the rst pin. 16.8 wait mode the wait instruction pu ts the mcu in low pow er-consumption standby mode. the cop continues to oper ate during wait mode. advance information mc68hc908mr24 ? rev. 4.1 342 computer operating properly (cop) freescale semiconductor computer operating properly (cop) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor external interrupt (irq) 343 advance information ? mc68hc908mr24 section 17. external interrupt (irq) 17.1 contents 17.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 17.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 17.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .344 17.5 irq pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 17.6 irq status and control register . . . . . . . . . . . . . . . . . . . . . . 348 17.2 introduction this section describes the external interrup t (irq) module, which supports external in terrupt functions. 17.3 features features of the irq module include: a dedicated external interrupt pin, irq hysteresis buffers advance information mc68hc908mr24 ? rev. 4.1 344 external interrupt (irq) freescale semiconductor external interrupt (irq) 17.4 functional description a logic 0 applied to any of the external interrupt pins can latch a cpu interrupt request. figure 17-1 shows the structur e of the irq module. interrupt signals on the irq pin are latched into the irq1 latch. an interrupt latch remains set until on e of the following actions occurs: vector fetch ? a vector fetch au tomatically generates an interrupt acknowledge signal that clears t he latch that caused the vector fetch. software clear ? software can clear an interrupt latch by writing to the appropriate ackn owledge bit in the in terrupt status and control register (iscr). writing a logic 1 to the a ck1 bit clears the irq1 latch. reset ? a reset automatically clears both interrupt latches. figure 17-1. irq module block diagram addr. register name bit 7654321bit 0 $003f irq status/control register (iscr) see page 348. read: 0000 irqf 0 imask1 mode1 write:rrrr ack1 reset:00000000 r= reserved figure 17-2. irq i/ o register summary ack1 imask1 dq ck clr irq high interrupt to mode select logic irq latch request irq v dd mode1 voltage detect synchro- nizer external interrupt (irq) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor external interrupt (irq) 345 the external interrupt pins are fa lling-edge-triggered and are software- configurable to be both falling- edge and low-level-triggered. the mode1 bit in the iscr controls the triggeri ng sensitivity of the irq pin. when the interrupt pin is edge-triggered only, the interr upt latch remains set until a vector fe tch, software clear, or reset occurs. when the interrupt pin is both fallin g-edge and low-leve l-triggered, the interrupt latch remains set until both of the following occur: vector fetch, software clear, or reset return of the interr upt pin to logic 1 the vector fetch or softwar e clear can occur before or after the interrupt pin returns to logic 1. as long as the pin is low, t he interrupt request remains pending. when set, the imask1 bi t in the iscr masks al l external interrupt requests. a latched interrupt request is not pres ented to the interrupt priority logic unless t he imask bit is clear. note: the interrupt mask (i) in the conditi on code register (ccr) masks all interrupt requests, including external inte rrupt requests. (see figure 17-3 .) advance information mc68hc908mr24 ? rev. 4.1 346 external interrupt (irq) freescale semiconductor external interrupt (irq) figure 17-3. irq interrupt flowchart from reset i bit set? fetch next yes no interrupt? instruction swi instruction? rti instruction? no stack cpu registers no set i bit load pc with interrupt vector no yes unstack cpu registers execute instruction yes yes external interrupt (irq) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor external interrupt (irq) 347 17.5 irq pin a logic 0 on the irq pin can latch an interrupt request into the irq latch. a vector fetch, software clear , or reset clears the irq latch. if the mode1 bit is set, the irq pin is both fa lling-edge-sensitive and low-level-sensitive. with mode1 se t, both of these actions must occur to clear the irq1 latch: vector fetch, software clear, or reset ? a vector fetch generates an interrupt acknowledge signal to clear the latch. software can generate the interrupt acknowledge si gnal by writing a logic 1 to the ack1 bit in the in terrupt status and cont rol register (iscr). the ack1 bit is useful in app lications that poll the irq pin and require software to clear the irq1 latch. writing to the ack1 bit can also prevent spurious interr upts due to noise . setting ack1 does not affect subsequent transitions on the irq pin. a falling edge that occurs after writing to the ack1 bit latches another interrupt request. if the irq1 ma sk bit, imask1, is clear, the cpu loads the program counter with th e vector address at locations $fffa and $fffb. return of the irq pin to logic 1 ? as long as the irq pin is at logic 0, the irq1 latch remains set. the vector fetch or software cl ear and the return of the irq pin to logic 1 can occur in any order. the inte rrupt request remains pending as long as the irq pin is at logic 0. if the mode1 bit is clear, the irq pin is falling-edge-sensitive only. with mode1 clear, a vector fe tch or software clear immediately clears the irq1 latch. use the bih or bil in struction to read the logic level on the irq pin. note: when using the level-sensit ive interrupt trigger, av oid false interrupts by masking interrupt requests in the interrupt routine. advance information mc68hc908mr24 ? rev. 4.1 348 external interrupt (irq) freescale semiconductor external interrupt (irq) 17.6 irq status and control register the irq status and control register (iscr) has t hese functions: clears the irq interrupt latch masks irq interrupt requests controls triggering se nsitivity of the irq interrupt pin ack1 ? irq interrupt request acknowledge bit writing a logic 1 to th is write-only bit clears the irq latch. ack1 always reads as logic 0. reset clears ack1. imask1 ? irq interrupt mask bit writing a logic 1 to this read/write bit disables irq interrupt requests. reset clears imask1. 1 = irq interrupt requests disabled 0 = irq interrupt requests enabled mode1 ? irq edge/ level select bit this read/write bit cont rols the triggering se nsitivity of the irq pin. reset clears mode1. 1 = irq interrupt requests on fa lling edges and low levels 0 = irq interrupt requests on falling edges only irqf ? irq flag this read-only bit acts as a status flag, indicating an irq event occurred. 1 = external irq event occurred 0 = external irq ev ent did not occur address: $003f bit 7654321bit 0 read: 0000 irqf 0 imask1 mode1 write:rrrr ack1 reset:00000000 r= reserved figure 17-4. irq status and control register (iscr) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor low-voltage inhibit (lvi) 349 advance information ? mc68hc908mr24 section 18. low-voltage inhibit (lvi) 18.1 contents 18.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 18.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 18.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .350 18.4.1 polled lvi operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 18.4.2 forced reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . .351 18.4.3 false reset protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 18.4.4 lvi trip selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 18.5 lvi status and control r egister . . . . . . . . . . . . . . . . . . . . . . . 352 18.6 lvi interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .353 18.7 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 18.2 introduction this section describes the low-vo ltage inhibit (lvi) module, which monitors the voltage on the v dd pin and can force a reset when the v dd voltage falls to t he lvi trip voltage. 18.3 features features of the lvi module include: programmable lvi reset programmable power consumption digital filtering of v dd pin level selectable lvi trip voltage advance information mc68hc908mr24 ? rev. 4.1 350 low-voltage inhibit (lvi) freescale semiconductor low-voltage inhibit (lvi) 18.4 functional description figure 18-1 shows the structur e of the lvi module. the lvi is enabled out of reset. the lvi module cont ains a bandgap reference circuit and comparator. the lvi power bit, lvipwr, enables the lvi to monitor v dd voltage. the lvi reset bit, lvirst, enables the lvi module to generate a reset when v dd falls below a voltage, v lvrx , and remains at or below that level for nine or more consecutive cgmxclk. v lvrx and v lvhx are determined by the trpsel bit in the lviscr (see figure 18-2 ). lvipwr and lvirst are in the conf iguration register (config). see section 5. configurat ion register (config) . once an lvi reset occurs, the mcu remains in reset until v dd rises above a voltage, v lvrx + v lvhx . v dd must be above v lvrx + v lvhx for only one cpu cycle to bring the mcu out of reset. see 7.4.2.5 low-voltage inhibit (lvi) reset . the output of the co mparator controls the state of the lviout flag in the lvi status register (lviscr). an lvi reset also drives the rst pin low to provide low-voltage protection to external peripheral devices. see 21.6 dc electrical characteristics (v dd = 5.0 vdc 10%) . figure 18-1. lvi module block diagram low v dd lvirst v dd > lvi trip = 0 v dd < lvi trip = 1 lviout lvipwr detector v dd lvi reset from config from config v dd digital filter cpu clock anlgtrip trpsel from lviscr low-voltage inhibit (lvi) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor low-voltage inhibit (lvi) 351 18.4.1 polled lvi operation in applications that can operate at v dd levels below v lvrx , software can monitor v dd by polling the lviout bit. in the configurati on register, the lvipwr bit must be at logic 1 to enable the lvi module, and the lvirst bit must be at logic 0 to disable lvi resets. see section 5. configuration register (config) . trpsel in the lviscr selects v lvrx . 18.4.2 forced reset operation in applications that require v dd to remain above v lvrx , enabling lvi resets allows the lvi module to reset the mcu when v dd falls to the v lvrx level and remains at or below that leve l for nine or more consecutive cpu cycles. in the mor, the lvip wr and lvirst bits must be at logic 0 to enable the lvi module and to enable lvi resets. trpsel in the lviscr selects v lvrx . 18.4.3 false reset protection the v dd pin level is digitally filtered to reduce false resets due to power supply noise. in order for the lvi module to reset the mcu,v dd must remain at or below v lvrx for nine or more c onsecutive cpu cycles. v dd must be above v lvrx + v lvhx for only one cpu cycle to bring the mcu out of reset. trpsel in the lviscr selects v lvrx + v lvhx . addr. register name bit 7654321bit 0 $fe0f lvi status and control register (lviscr) see page 352. read: lviout 0 trpsel 00000 write:rr rrrrr reset:00000000 r=reserved figure 18-2. lvi i/ o register summary advance information mc68hc908mr24 ? rev. 4.1 352 low-voltage inhibit (lvi) freescale semiconductor low-voltage inhibit (lvi) 18.4.4 lvi trip selection the trpsel bit allows the user to chose between 5 percent and 10 percent tolerance when monito ring the supply voltage. the 10 percent option is enabl ed out of reset. writi ng a logic 1 to trpsel will enable 5 perc ent option. note: the microcontroller is guaranteed to operate at a minimum supply voltage. the trip point (v lvr1 or v lvr2 ) may be lowe r than this. see 21.6 dc electrical c haracteristics (v dd = 5.0 vdc 10%) . 18.5 lvi status an d control register the lvi status register (lviscr) flags v dd voltages below the v lvrx level . lviout ? lvi output bit this read-only flag be comes set when the v dd voltage falls below the v lvrx voltage for 32 to 40 cgmxclk cycles. see table 18-1 . reset clears the lviout bit. address: $fe0f bit 7654321bit 0 read: lviout 0 trpsel 00000 write:rr rrrrr reset:00000000 r=reserved figure 18-3. lvi status and co ntrol register (lviscr) low-voltage inhibit (lvi) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor low-voltage inhibit (lvi) 353 trpsel ? lvi trip select bit this bit selects the lvi trip poi nt. reset clears this bit. 1 = 5 percent toleranc e. the trip point and recovery point are determined by v lvr1 and v lvh1 , respectively. 0 = 10 percent tolerance. the tr ip point and recovery point are determined by v lvr2 and v lvh2 , respectively. note: if lvirst and lvipwr are at logi c 0, note that when changing the tolerence, lvi re set will be generated if the supply voltage is below the trip point. 18.6 lvi interrupts the lvi module does not gener ate interrupt requests. table 18-1. lviout bit indication v dd lviout at level: for number of cgmxclk cycles: v dd > v lv r x + v lv h x any 0 v dd < v lv r x < 32 cgmxclk cycles 0 v dd < v lv r x between 32 & 40 cgmxclk cycles 0 or 1 v dd < v lv r x > 40 cgmxclk cycles 1 v lvr x < v dd < v lv r x + v lv h x any previous value advance information mc68hc908mr24 ? rev. 4.1 354 low-voltage inhibit (lvi) freescale semiconductor low-voltage inhibit (lvi) 18.7 wait mode the wait instruction pu ts the mcu in low pow er-consumption standby mode. with the lvipwr bit in the configuration register programmed to logic 1, the lvi module is active after a wait instruction. with the lvirst bit in the configurat ion register program med to logic 1, the lvi module c an generate a reset and bring the mcu out of wait mode. mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor analog-to-digital converter (adc) 355 advance information ? mc68hc908mr24 section 19. analog-to-digital converter (adc) 19.1 contents 19.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 19.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 19.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .356 19.4.1 adc port i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 19.4.2 voltage conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358 19.4.3 conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 19.4.4 continuous conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 19.4.5 result justification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 19.4.6 monotonicity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 19.5 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .361 19.6 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 19.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 19.7.1 adc analog power pin (v ddad ) . . . . . . . . . . . . . . . . . . . . 361 19.7.2 adc analog ground pin (v ssad ). . . . . . . . . . . . . . . . . . . .362 19.7.3 adc voltage reference pin (v refh ) . . . . . . . . . . . . . . . . . 362 19.7.4 adc voltage reference low pin (v refl ) . . . . . . . . . . . . . 362 19.7.5 adc voltage in ( advin) . . . . . . . . . . . . . . . . . . . . . . . . . . 362 19.7.6 adc external connections. . . . . . . . . . . . . . . . . . . . . . . . . 362 19.7.6.1 v reff and v refl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 19.7.6.2 anx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 19.7.6.3 grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 19.8 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 19.8.1 adc status and control register. . . . . . . . . . . . . . . . . . . .364 19.8.2 adc data register high . . . . . . . . . . . . . . . . . . . . . . . . . . 367 19.8.3 adc data register low . . . . . . . . . . . . . . . . . . . . . . . . . . .368 19.8.4 adc clock register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 advance information mc68hc908mr24 ? rev. 4.1 356 analog-to-digital converter (adc) freescale semiconductor analog-to-digital converter (adc) 19.2 introduction this section describes th e 10-bit analog-to-digit al converter (adc). 19.3 features features of the ad c module include: 10 channels with multiplexed input linear successive approximation 10-bit resolution, 8-bit accuracy single or cont inuous conversion conversion complete flag or conversion complete interrupt selectable adc clock left or right justified result left justified sign data mode high impedance buf fered adc input 19.4 functional description ten adc channels are availa ble for sampling extern al sources at pins ptc1/atd9:ptc0/atd8 and ptb7/a td7:ptb0/atd0. to achieve the best possible accuracy, these pins are implemented as input-only pins when the analog-to-digital (a/d) feature is enabl ed. an analog multiplexer allows the single adc conv erter to select one of the 10 adc channels as adc voltage in (adcvin). adcvin is converted by the successive approximation algorithm. when the conv ersion is completed, the adc places the result in t he adc data register (adrh and adrl) and sets a flag or generat es an interrupt. see figure 19-1 . analog-to-digital converter (adc) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor analog-to-digital converter (adc) 357 figure 19-1. adc block diagram 19.4.1 adc port i/o pins ptc1/atd9:ptc0/atd8 and pt b7/atd7:ptb0/atd0 are general-purpose i/o pins that are shared with the adc channels. the channel select bits define whic h adc channel/por t pin will be used as the input signal. the adc overrides the port logic when that port is selected by the adc mux. the rema ining adc channels/ port pins are controlled by the port logic and can be used as general-purpose input/output (i/o) pins. writes to t he port register or ddr will not have any affect on the port pin that is se lected by the adc. r ead of a port pin which is in use by the adc will return a logic 0. internal data bus read ptb/ptc ptb/cx interrupt logic channel select adc clock generator conversion complete adc voltage in advin adc clock cgmxclk bus clock adch[4:0] adc data registers adiv[2:0] adiclk aien coco/idmas disable adc channel x ptx advance information mc68hc908mr24 ? rev. 4.1 358 analog-to-digital converter (adc) freescale semiconductor analog-to-digital converter (adc) 19.4.2 voltage conversion when the input voltage to the adc equals v refh , the adc converts the signal to $3ff (full scale). if the input voltage equals v refl , the adc converts it to $000. input voltages between v refh and v refl are straight-line linear conversions. all ot her input voltages will result in $3ff if greater than v refh and $000 if less than v refl . note: input voltage should not exceed the analog supply voltages. see 21.14 analog-to-digital converter (adc) characteristics . 19.4.3 conversion time conversion starts after a write to the adscr. a conversion is between 16 and 17 adc clock cycles, therefore: the adc conversion time is determine d by the clock so urce chosen and the divide ratio selected. the clock s ource is either the bus clock or cgmxclk and is selectabl e by adiclk located in the adc clock register. for exampl e, if cgmxclk is 4 mhz and is selected as the adc input clock source, the adc input clo ck divide-by-2 presca le is selected and the bus frequency is 8 mhz: note: the adc frequency must be between f adic minimum and f adic maximum to meet a/d specifications. see 21.14 analog-to-digital converter (adc) characteristics . since an adc cycle may be comprised of several bus cycles (four in the previous example) and t he start of a conversion is initiated by a bus cycle write to the adscr, from zero to four additional bus cycles may occur 16 to17 adc cycles conversion time = adc frequency number of bus cycles = conv ersion time x bus frequency 16 to17 adc cycles conversion time = 4 mhz/2 number of bus cycles = 8 s x 8 mhz = 64 to 68 cycles = 8 to 8.5 s analog-to-digital converter (adc) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor analog-to-digital converter (adc) 359 before the start of the in itial adc cycle. this resu lts in a fractional adc cycle and is represented as the ?17th? cycle. 19.4.4 continuous conversion in the continuous conv ersion mode, the adc dat a registers adrh and adrl will be filled with new data after each conv ersion. data from the previous conversion will be overwritt en whether that dat a has been read or not. conversions wil l continue until the adco bit is cleared. the coco bit is set after t he first conversion and will stay set for the next several conversions until the next wr ite of the adc st atus and control register or the next read of the adc dat a register. 19.4.5 result justification the conversion result may be form atted in four different ways: left justified right justified left justified sign data mode 8-bit truncation mode all four of these modes are controlled using mode0 and mode1 bits located in the adc cl ock register (adcr). left justification wi ll place the eight most signi ficant bits (msb) in the corresponding adc data r egister high, a drh. this may be useful if the result is to be treated as an 8-bit result where the tw o least significant bits (lsb), located in the adc data register lo w, adrl, can be ignored. however, adrl must be read after adrh or else the interlocking will prevent all new conver sions from being stored. right justification will place only t he two msbs in the corresponding adc data register high, adrh, and the eight lsbs in adc dat a register low, adrl. this mode of operation typica lly is used when a 10-bit unsigned result is desired. advance information mc68hc908mr24 ? rev. 4.1 360 analog-to-digital converter (adc) freescale semiconductor analog-to-digital converter (adc) left justified sign data mode is simi lar to left justified mode with one exception. the msb of the 10-bit re sult, ad9 located in adrh, is complemented. this m ode of operation is useful when a result, represented as a signed magnitude from mid-scale , is needed. finally, 8-bit truncation mode will place the eight msbs in adc data register low, adrl. the two lsbs are dropped. thi s mode of operation is used when compatibility with 8-bit adc desi gns are required. no interlocking between adrh and adrl is present. note: quantization error is affe cted when only the most significant eight bits are used as a result. see figure 19-2 . figure 19-2. 8-bit tr uncation mode error ideal 10-bit characteristic with quantization = 1/2 ideal 8-bit characteristic with quantization = 1/2 10-bit truncated to 8-bit result when truncation is used, error from ideal 8-bit = 3/8 lsb due to non-ideal quantization. 000 001 002 003 004 005 006 007 008 009 00a 00b 000 001 002 003 8-bit result 10-bit result input voltage represented as 10-bit input voltage represented as 8-bit 1/2 2 1/2 4 1/2 6 1/2 8 1/2 1 1/2 3 1/2 5 1/2 7 1/2 9 1/2 1/2 2 1/2 1 1/2 analog-to-digital converter (adc) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor analog-to-digital converter (adc) 361 19.4.6 monotonicity the conversion process is monot onic and has no missing codes. 19.5 interrupts when the aien bit is se t, the adc module is capable of generating a cpu interrupt after each adc conversion. a cpu interrupt is generated if the coco bit is at logic 0. the coco bit is not used as a conversion complete flag when interrupts are enabled. 19.6 wait mode the wait instruction can put the mcu in low power-consumption standby mode. the adc continues norma l operation during wait mode. any enabled cpu interrupt request fro m the adc can bring t he mcu out of wait mode. if the adc is not required to bring the mcu out of wait mode, power down the adc by se tting adch[4:0] in the adc status and control register before executin g the wait instruction. 19.7 i/o signals the adc module has 10 i nput signals that are shared with port b and port c. 19.7.1 adc analog power pin (v ddad ) the adc analog portion uses v ddad as its power pin. connect the v ddad pin to the same voltage potential as v dd . external filtering may be necessary to ensure clean v ddad for good results. note: route v ddad carefully for maximum noise immunity and place bypass capacitors as close as possible to the package. advance information mc68hc908mr24 ? rev. 4.1 362 analog-to-digital converter (adc) freescale semiconductor analog-to-digital converter (adc) 19.7.2 adc analog ground pin (v ssad ) the adc analog portion uses v ssad as its ground pi n. connect the v ssad pin to the same voltage potential as v ss . 19.7.3 adc voltage reference pin (v refh ) v refh is the power supply for sett ing the reference voltage v refh . connect the v refh pin to the same voltage potential as v ddad . there will be a finite current associated with v refh . see section 21. electrical specifications . note: route v refh carefully for maximum nois e immunity and place bypass capacitors as close as possible to the package. 19.7.4 adc voltage reference low pin (v refl ) v refl is the lower reference supp ly for the adc. connect the v refl pin to the same voltage potential as v ssad . a finite current will be associated with v refl . see section 21. electr ical specifications . note: in the 56-pin shri nk dual in-line package (sdip), v refl and v ssad are tied together. 19.7.5 adc volt age in (advin) advin is the input vo ltage signal from one of t he 10 adc channels to the adc module. 19.7.6 adc external connections this section describes the adc external connections: v refh and v refl , anx, and grounding. analog-to-digital converter (adc) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor analog-to-digital converter (adc) 363 19.7.6.1 v refh and v refl both ac and dc current are drawn through the v refh and v refl loop. the ac current is in the form of curr ent spikes required to supply charge to the capacitor array at each successive approximation step. the current flows through the internal resistor stri ng. the best external component to meet both these current demands is a c apacitor in the 0.01 f to 1 f range with good high frequency characteristics. this capacitor is connected between v refh and v refl and must be placed as close as possible to the package pins. resistance in the path is not recommended because the dc current will caus e a voltage drop which could result in conversion errors. 19.7.6.2 anx empirical data shows that capacit ors from the analog inputs to v refl improve adc performance. 0.01 f and 0.1 f capacitors with good high-frequency characteri stics are sufficient. these capacitors must be placed as close as possi ble to the package pins. 19.7.6.3 grounding in cases where separate power supp lies are used for analog and digital power, the ground connection between t hese supplies should be at the v ssa pin. this should be the onl y ground connection between these supplies if possible. the v ssa pin makes a good single point ground location. connect the v refl pin to the same potential as v ssad at the single point ground location. 19.8 i/o registers these i/o registers control and monitor operati on of the adc: adc status and cont rol register, adscr adc data regist ers, adrh and ardl adc clock register, adclk advance information mc68hc908mr24 ? rev. 4.1 364 analog-to-digital converter (adc) freescale semiconductor analog-to-digital converter (adc) 19.8.1 adc status and control register this section describes the functi on of the adc st atus and control register (adscr). writ ing adscr aborts the current conversion and initiates a new conversion. coco ? conversions complete bit when aien bit is a logi c 0, the coco is a r ead-only bit which is set each time a conversion is comple ted except in the continuous conversion mode where it is set after the first c onversion. this bit is cleared whenever the adc status and control regi ster is written or whenever the adc data register is read. if aien bit is a logic 1, the coco is a read/writ e bit. reset clears this bit. 1 = conversion comp leted (aien = 0) 0 = conversion not completed (aie n = 0)/cpu interrupt (aien = 1) aien ? adc interrupt enable bit when this bit is set, an interrupt is generated at the end of an adc conversion. the interrupt signal is cl eared when the dat a register is read or the status/control register is written. re set clears the aien bit. 1 = adc interrupt enabled 0 = adc interrupt disabled address: $0040 bit 7654321bit 0 read: coco aien adco adch4 adch3 adch2 adch1 adch0 write: reset:00011111 figure 19-3. adc status and contro l register (adscr) analog-to-digital converter (adc) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor analog-to-digital converter (adc) 365 adco ? adc continuous conversion bit when set, the adc will convert sa mples continuously and update the adr register at the end of each conversion. only one conversion is allowed when this bit is cleared. reset clears the adco bit. 1 = continuous adc conversion 0 = one adc conversion adch[4:0] ? adc channel select bits adch4, adch3, adch2, adch1, and adch0 fo rm a 5-bit field which is used to select one of 10 adc channels. the adc channels are detailed in table 19-1 . note: take care to prevent s witching noise from co rrupting the analog signal when simultaneously using a port pin as both an analog and digital input. the adc subsystem is turned off when t he channel select bits are all set to 1. this feature a llows for reduced power c onsumption for the mcu when the adc is not used. note: recovery from the disabled stat e requires one conversion cycle to stabilize. the voltage levels supplied from internal reference nodes as specified in table 19-1 are used to verify the operat ion of the adc both in production test and for user applications. advance information mc68hc908mr24 ? rev. 4.1 366 analog-to-digital converter (adc) freescale semiconductor analog-to-digital converter (adc) table 19-1. mux channel select adch4 adch3 adch2 adch1 adch0 input select 00000 ptb0/atd0 00001 ptb1/atd1 00010 ptb2/atd2 00011 ptb3/atd3 00100 ptb4/atd4 00101 ptb5/atd5 00110 ptb6/atd6 00111 ptb7/atd7 01000 ptc0/atd8 01001ptc1/atd9 *** 01010 unused * 01011 ? 01100 ? 01101 ? 01110 ? 01111 ? 10000 ? 11010 unused * 11011 reserved ** 1 1 1 0 0 unused * 1 1 1 0 1 v refh 1 1 1 1 0 v refl 1 1 1 1 1 [adc power off] * if any unused channels are selected, the resulting adc conversion will be unknown. ** used for factory testing. *** atd9 is not avialable in the 56-pin sdip package. analog-to-digital converter (adc) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor analog-to-digital converter (adc) 367 19.8.2 adc data register high in left justified m ode, this 8-bit result register holds the eight msbs of the 10-bit result. this register is u pdated each time an adc single channel conversion completes. reading ad rh latches the contents of adrl until adrl is read. until adrl is read, all subsequent adc results will be lost. in right justified m ode, this 8-bit result register holds the two msbs of the 10-bit result. all other bits read as 0. this register is updated each time a single channel adc conversion co mpletes. reading adrh latches the contents of adrl unt il adrl is read. until ad rl is read, all subsequent adc results will be lost. address: $0041 bit 7654321bit 0 read: ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 write:rrrrrrrr reset: unaffected by reset r= reserved figure 19-4. adc data register high (adrh) left justified mode address: $0041 bit 7654321bit 0 read: 000000ad9ad8 write:rrrrrrrr reset: unaffected by reset r= reserved figure 19-5. adc data register high (adrh) right justified mode advance information mc68hc908mr24 ? rev. 4.1 368 analog-to-digital converter (adc) freescale semiconductor analog-to-digital converter (adc) 19.8.3 adc data register low in left justified mode, this 8-bit resu lt register holds t he two lsbs of the 10-bit result. all other bits read as 0. this register is updated each time a single channel adc conversion co mpletes. reading adrh latches the contents of adrl unt il adrl is read. until ad rl is read, all subsequent adc results will be lost. in right justified mode, th is 8-bit result register holds the eight lsbs of the 10-bit result. this register is updated each time an adc conversion completes. reading adrh latches th e contents of adrl until adrl is read. until adrl is r ead, all subsequent adc re sults will be lost. address: $0042 bit 7654321bit 0 read: ad1 ad0 000000 write:rrrrrrrr reset: unaffected by reset r= reserved figure 19-6. adc data register low (adrl) left justified mode address: $0042 bit 7654321bit 0 read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write:rrrrrrrr reset: unaffected by reset r= reserved figure 19-7. adc data register low (adrl) right justified mode analog-to-digital converter (adc) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor analog-to-digital converter (adc) 369 in 8-bit mode, this 8-bit result regist er holds the eight ms bs of the 10-bit result. this register is updated each ti me an adc conversion completes. in 8-bit mode, this register contains no interlocking with adrh. 19.8.4 adc clock register this register selects th e clock frequency for the adc, selecting between modes of operation. adiv2:adiv0 ? adc cl ock prescaler bits adiv2, adiv1, and adiv0 form a 3-bit field wh ich selects the divide ratio used by the a dc to generate the in ternal adc clock. table 19-2 shows the available clock configurations. address: $0042 bit 7654321bit 0 read: ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 write:rrrrrrrr reset: unaffected by reset r= reserved figure 19-8. adc data regist er low (adrl) 8-bit mode address: $0043 bit 7654321bit 0 read: adiv2 adiv1 adiv0 adiclk mode1 mode0 0 0 write: r reset:01110000 r= reserved figure 19-9. adc clock register (adclk) advance information mc68hc908mr24 ? rev. 4.1 370 analog-to-digital converter (adc) freescale semiconductor analog-to-digital converter (adc) adiclk ? adc input clock select bit adiclk selects either bus clock or cgmxclk as the input clock source to generate the internal adc clock. reset selects cgmxclk as the adc clock source. if the external clock (cgmxclk) is equal to or grea ter than 1 mhz, cgmxclk can be used as the cl ock source for the adc. if cgmxclk is less than 1 mhz, use the pll-generated bus clock as the clock source. as long as t he internal adc clock is at f adic , correct operation can be guaranteed. see 21.14 analog-to-digital converter (adc) characteristics . 1 = internal bus clock 0 = external clock, cgmxclk mode1:mode0 ? modes of result justification mode1:mode0 selects between f our modes of operation. the manner in which the adc conversion re sults will be placed in the adc data registers is controlled by t hese modes of operation. reset returns right-justified mode. 00 = 8-bit truncation mode 01 = right justified mode 10 = left just ified mode 11 = left justifie d sign data mode table 19-2. adc clock divide ratio adiv2 adiv1 adiv0 adc clock rate 0 0 0 adc input clock /1 0 0 1 adc input clock /2 0 1 0 adc input clock /4 0 1 1 adc input clock /8 1 x x adc input clock /16 x = don?t care cgmxclk or bus frequency f adic = adiv[2:0] mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor power-on reset (por) 371 advance information ? mc68hc908mr24 section 20. power-on reset (por) 20.1 contents 20.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 20.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .371 20.2 introduction this section describes the power-on reset (por) module. 20.3 functional description the por module provides a known, st able signal to the mcu at power- on. this signal tracks v dd until the mcu generates a feedback signal to indicate that it is pro perly initialized. at this time, the por drives its output low. the por is not a brown-out detector, low-voltage detector, or glitch detector. v dd at the por must go completely to 0 to reset the mcu. to detect power-loss conditions, use a lo w-voltage inhibit module (lvi) or other suitable circuit. advance information mc68hc908mr24 ? rev. 4.1 372 power-on reset (por) freescale semiconductor power-on reset (por) mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor electrical specifications 373 advance information ? mc68hc908mr24 section 21. electrical specifications 21.1 contents 21.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 21.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 374 21.4 functional operating range. . . . . . . . . . . . . . . . . . . . . . . . . . 375 21.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 21.6 dc electrical characteristics (v dd = 5.0 vdc 10%). . . . . . . 376 21.7 flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . 377 21.8 control timing (v dd = 5.0 vdc 10%) . . . . . . . . . . . . . . . . . 378 21.9 serial peripheral inte rface characteristics (v dd = 5.0 vdc 10%) . . . . . . . . . . . . . . . . . . . . . . . . . . .379 21.10 timer interface module characterist ics . . . . . . . . . . . . . . . . . 382 21.11 clock generation m odule component specific ations . . . . . . 382 21.12 cgm operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . .382 21.13 cgm acquisition/lock ti me specifications . . . . . . . . . . . . 383 21.14 analog-to-digital converter (adc) characteristics. . . . . . . . . 384 21.2 introduction this section contains electrical and timing specifications. these values are design targets and have no t yet been fully characterized. advance information mc68hc908mr24 ? rev. 4.1 374 electrical specifications freescale semiconductor electrical specifications 21.3 absolute maximum ratings maximum ratings are t he extreme limits to which the mcu can be exposed without perman ently damaging it. note: this device is not guar anteed to operate properly at the maximum ratings. for guaran teed operating conditions, refer to 21.6 dc electrical characteristics (v dd = 5.0 vdc 10%) . note: this device contains circ uitry to protect the i nputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid applic ation of any voltage higher than maximum-rated voltages to this hi gh-impedance circui t. for proper operation, it is recommended that v in be constrained to the range v ss (v in ) v dd . reliability of operation is enhanced if unused inputs are connected to an appr opriate logic voltage level (for example, either v ss or v dd ). characteristic (1) 1. voltages referenced to v ss . symbol value unit supply voltage v dd ?0.3 to +6.0 v input voltage v in v ss ?0.3 to v dd +0.3 v input high voltage v hi v dd + 4 maximum v maximum current per pin excluding v dd and v ss i 25 ma storage temperature t stg ?55 to +150 c maximum current out of v ss i mvss 100 ma maximum current into v dd i mvdd 100 ma electrical specifications mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor electrical specifications 375 21.4 functional operating range 21.5 thermal characteristics characteristic symbol value unit operating temperature range (see notes) mc68hc908mr24cfu mc68hc908mr24vfu t a ?40 to 85 ?40 to 105 c operating voltage range v dd 5.0 10% v notes: see freescale representative for temperature availability. c = extended temperature range (?40 c to +85 c) v = automotive temperature range (?40 c to +105 c) characteristic symbol value unit thermal resistance, 64-pin qfp ja 76 c/w i/o pin power dissipation p i/o user determined w power dissipation (1) 1. power dissipation is a function of temperature. p d p d = (i dd x v dd ) + p i/o = k/(t j + 273 c) w constant (2) 2. k is a constant unique to the device. k can be determined for a known t a and measured p d. with this value of k, p d and t j can be determined for any value of t a . k p d x (t a + 273 c ) + p d 2 x ja w/ c average junction temperature t j t a + (p d x ja ) c maximum junction temperature t jm 125 c advance information mc68hc908mr24 ? rev. 4.1 376 electrical specifications freescale semiconductor electrical specifications 21.6 dc electrical characteristics (v dd = 5.0 vdc 10%) characteristic min typ (2) max unit output high voltage (i load = ?2.0 ma) all i/o pins v oh v dd ?0.8 ? ? v output low voltage (i load = 1.6 ma) all i/o pins v ol ??0.4v pwm pin output source current (v oh = v dd ?0.8 v) i oh ?7 ? ? ma pwm pin output sink current (v ol = 0.8 v) i ol 20 ? ? ma input high voltage, all ports, irqs, reset, osc1 v ih 0.7 x v dd ?v dd v input low voltage, all ports, irqs, reset, osc1 v il v ss ? 0.3 x v dd v v dd supply current run (3) wait (4) quiescent (5) i dd ? ? ? ? ? ? 40 20 700 ma ma a i/o ports hi-z leakage current i il ?? 10 a input current i in ?? 1 a capacitance ports (as input or output) c out c in ? ? ? ? 12 8 pf low-voltage inhibit reset 9 v lvr1 4.33 4.45 4.75 v low-voltage reset/recover hysteresis v lvh1 50 100 ? mv low-voltage inhibit reset v lvr2 3.95 ? 4.35 v low-voltage reset/recover hysteresis v lvh2 150 ? 250 mv por re-arm voltage (6) v por 0?100mv por rise time ramp rate (8) r por 0.035 ? ? v/ms por reset voltage v porrst 0 700 800 v monitor mode entry voltage (on irq) v hi v dd + 2 ? v dd + hi v 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h , unless otherwise noted 2. typical values reflect average measur ements at midpoint of voltage range, 25 c only. 3. run (operating) i dd measured using external square wave clock source (f osc = 8.2 mhz). all inputs 0.2 v from rail; no dc loads; less than 100 pf on all outputs. c l = 20 pf on osc2; all ports configured as inputs; osc2 capacitance linearly affects run i dd ; measured with all modules enabled. 4. wait i dd measured using external square wave clock source (f osc = 8.2 mhz); all inputs 0.2 v from rail; no dc loads; less than 100 pf on all outputs. c l = 20 pf on osc2; all ports configured as inputs; osc2 capacitance linearly affects wait i dd ; measured with pll and lvi enabled. 5. quiescent i dd measured with pll and lvi disengaged, ocs1 grounded, no port pins sourcing current. it is measured through combination of v dd , v ddad , and v dda . 6. maximum is highest volt age that por is guaranteed. 7. maximum is highest voltage that por is possible. 8. if minimum v dd is not reached before the internal por is released, rst must be driven low externally until minimum v dd is reached 9. the low-voltage inhibit reset is software selectable. refer to section 18. low-voltage inhibit (lvi) . electrical specifications mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor electrical specifications 377 21.7 flash memory characteristics characteristic symbol/ description min max units flash pages per row 8 8 pages flash bytes per page 8 8 bytes flash read bus clock frequency f read (1) 1. f read is defined as the frequency range for which the flash memory can be read. 32 k 8.4 m hz flash charge pump clock frequency (see 4.5 flash charge pump frequency control ) f pump (2) 2. f pump is defined as the charge pump clock frequency r equired for program, erase, and margin read operations. 1.8 2.5 mhz flash block/bulk erase time t erase 100 ? ms flash high-voltage kill time t kill 200 ? s flash return to read time t hvd 50 ? s flash page program pulses fls pulses (3) 3. fls pulses is defined as the number of pulses used to progra m the flash using the required smart program algorithm. ? 100 pulses flash page program step size t prog (4) 4. t step is defined as the amount of time during one pag e program cycle that hven is held high. 1.0 1.2 ms flash cumulative program operation per row between erase cycles t row (5) 5. t row is defined as the cumulative time a row can see the program voltage before the row must be erased before further programming. ?8 page programming cycles flash hven low to margin high time t hvtv 50 ? s flash margin high to pgm low time t vtp 150 ? s flash row erase endurance (6) 6. the minimum row endurance value specifies each row of the flash memory is guaranteed to work for at least this many erase/program cycles. ? 100 ? cycles flash row program endurance (7) 7. the minimum row endurance value specifies each row of the flash memory is guaranteed to work for at least this many erase/program cycles. ? 100 ? cycles flash data retention time (8) 8. the flash is guaranteed to retain data over the entire temperat ure range for at least the minimum time specified. ?10? years advance information mc68hc908mr24 ? rev. 4.1 378 electrical specifications freescale semiconductor electrical specifications 21.8 control timing (v dd = 5.0 vdc 10%) characteristic (1) 1. v ss = 0 vdc; timing shown with respect to 20% v dd and 70% v dd , unless otherwise noted symbol min max unit frequency of operation (2) crystal option external clock option (3) 2. see 21.9 serial peripheral interface characteristics (v dd = 5.0 vdc 10%) for more information. 3. no more than 10% duty cycle deviation from 50%. f osc 1 dc (4) 4. some modules may require a minimum frequency greater than dc for proper operation; s ee appropriate table for this information. 8 32.8 mhz internal operating frequency f op ?8.2mhz reset input pulse width low (5) 5. minimum pulse width reset is guaranteed to be recognized. it is possible for a smaller pulse width to cause a reset. t irl 50 ? ns electrical specifications mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor electrical specifications 379 21.9 serial peripheral interface characteristics (v dd = 5.0 vdc 10%) diagram number (1) 1. all timing is shown with respect to 20% v dd and 70% v dd , unless otherwise noted; assumes 100 pf load on all spi pins characteristic (2) 2. numbers refer to dimensions in figure 21-1 and figure 21-2 . symbol min max unit operating frequency master slave f op(m) f op(s) f op /128 dc f op /2 f op mhz 1 cycle time master slave t cyc(m) t cyc(s) 2 1 128 ? t cyc 2 enable lead time t lead(s) 15 ? ns 3 enable lag time t lag(s) 15 ? ns 4 clock (spck) high time master slave t sckh(m) t sckh(s) 100 50 ? ? ns 5 clock (spck) low time master slave t sckl(m) t sckl(s) 100 50 ? ? ns 6 data setup time (inputs) master slave t su(m) t su(s) 45 5 ? ? ns 7 data hold time (inputs) master slave t h(m) t h(s) 0 15 ? ? ns 8 access time, slave (3) cpha = 0 chpa = 1 3. time to data active from high-impedance state t a(cp0) t a(cp1) 0 0 40 20 ns 9 disable time, slave (4) 4. hold time to high-impedance state t dis(s) ?25ns 10 data valid time after enable edge master slave (5) 5. with 100 pf on all spi pins t v(m) t v(s) ? ? 10 40 ns advance information mc68hc908mr24 ? rev. 4.1 380 electrical specifications freescale semiconductor electrical specifications figure 21-1. spi master timing note ss pin of master held high msb in ss input spck, cpol = 0 output spck, cpol = 1 output miso input mosi output note 4 5 5 1 4 bits 6?1 lsb in master msb out bits 6?1 master lsb out 10 11 10 11 7 6 note note: this last clock edge is generated inte rnally, but is not seen at the sck pin. ss pin of master held high msb in ss input spck, cpol = 0 output spck, cpol = 1 output miso input mosi output note 4 5 5 1 4 bits 6?1 lsb in master msb out bits 6?1 master lsb out 10 11 10 11 7 6 a) spi master timing (cpha = 0) b) spi master timing (cpha = 1) note: this first clock edge is generated internally, but is not seen at the sck pin. electrical specifications mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor electrical specifications 381 figure 21-2. spi slave timing note: not defined, but normally msb of character just received slave ss input spck, cpol = 0 input spck, cpol = 1 input miso input mosi output 4 5 5 1 4 msb in bits 6?1 8 6 10 11 11 note slave lsb out 9 3 lsb in 2 7 bits 6?1 msb out note: not defined, but normally lsb of character previ ously transmitted slave ss input spck, cpol = 0 input spck, cpol = 1 input miso output mosi input 4 5 5 1 4 msb in bits 6?1 8 6 10 note slave lsb out 9 3 lsb in 2 7 bits 6?1 msb out 10 a) spi slave timing (cpha = 0) b) spi slave timing (cpha = 1) 11 11 advance information mc68hc908mr24 ? rev. 4.1 382 electrical specifications freescale semiconductor electrical specifications 21.10 timer interface module characteristics 21.11 clock generation modu le component specifications 21.12 cgm operating conditions characteristic symbol min max unit input capture pulse width t tih, t til 125 ? ns input clock pulse width t tch, t tcl (1/f op ) + 5 ?ns characteristic symbol min typ max notes crystal load capacitance c l ??? consult crystal manufacturing data crystal fixed capacitance c 1 ? 2 * c l ? consult crystal manufacturing data crystal tuning capacitance c 2 ? 2 * c l ? consult crystal manufacturing data feedback bias resistor r b ?22 m ? ? series resistor r s 0330 k ? 1 m ? not required filter capacitor c f ? c fact * (v dda /f xclk ) ? bypass capacitor c byp ?0.1 f? c byp must provide low ac impedance from f = f xclk /100 to 100*f vclk , so series resistance must be considered characteristic symbol min typ max crystal reference frequency f xclk 1 mhz ? 8 mhz range nominal multiplier f nom ? 4.9152 mhz ? vco center-of-range frequency f vrs 4.9152 mhz ? 32.8 mhz vco frequency multiplier n1 ?15 vco center of range multiplier l1 ?15 vco operating frequency f vclk f vrsmin ?f vrsmax electrical specifications mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor electrical specifications 383 21.13 cgm acquisition/lo ck time specifications description symbol min typ max notes filter capacitor multiply factor c fact ?0.0154? f/sv acquisition mode time factor k acq ?0.1135? v tracking mode time factor k trk ?0.0174? v manual mode time to stable t acq ? (8*v dda )/ (f x clk *k acq) ? if c f chosen correctly manual stable to lock time t al ? (4*v dda )/ (f x clk *k trk ) ? if c f chosen correctly manual acquisition time t lock ? t acq +t al ? tracking mode entry frequency to l e r a n c e ? trk 0? 3.6% acquisition mode entry frequency to l e r a n c e ? acq 6.3% ? 7.2% lock entry frequency tolerance ? lock 0? 0.9% lock exit frequency tolerance ? unl 0.9% ? 1.8% reference cycles per acquisition mode measurement n acq ?32? reference cycles per tracking mode measurement n trk ?128? automatic mode time to stable t acq n acq /f xclk (8*v dda )/ (f x clk *k acq) ? if c f chosen correctly automatic stable to lock time t al n trk /f xclk (4*v dda )/ (f x clk *k trk ) ? if c f chosen correctly automatic lock time t lock ? t acq +t al ? pll jitter (deviation of average bus frequency over 2 ms) f j 0? (f xclk ) *(0.025%) *(n/4) n = vco freq. mult. advance information mc68hc908mr24 ? rev. 4.1 384 electrical specifications freescale semiconductor electrical specifications 21.14 analog-to-digital co nverter (adc) characteristics characteristic symbol min typ max unit notes supply voltage v ddad 4.5 ? 5.5 v v ddad should be tied to the same potential as v dd via separate traces input voltages v adin 0? v ddad v v adin <= v ddad resolution b ad 10 ? 10 bits absolute accuracy a ad ?? 4 counts includes quantization adc internal clock f adic 500 k ? 1.048 m hz t aic = 1/f adic conversion range r ad v ssad ? v ddad v power-up time t adpu 16 ? ? t aic cycles conversion time t adc 16 ? 17 t aic cycles sample time t ads 5? ? t aic cycles monotonicity m ad guaranteed zero input reading z adi 000 ? 003 hex v adin = v ssad full-scale reading f adi 3fc ? 3ff hex v adin = v ddad input capacitance c adi ? ? 30 pf not tested v refh /v refl current i vref ?1.6 ? ma absolute accuracy (8-bit truncation mode) a ad ?? 1 lsb includes quantization quantization error (8-bit truncation mode) ??? +7/8 ?1/8 lsb mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor mechanical specifications 385 advance information ? mc68hc908mr24 section 22. mechanical specifications 22.1 contents 22.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 22.3 64-pin plastic quad flat pack (qfp) . . . . . . . . . . . . . . . . . . . 386 22.4 56-pin shrink dual in -line package (sdip) . . . . . . . . . . . . . . 387 22.2 introduction this section gives the di mensions for the 64-lead plastic quad flat pack (qfp) and 56-pin shrink dual in-line package (sdip). figure 22-1 and figure 22-2 show the latest package at the time of this publication. to make sure that you have the latest package specifications, please visi t the freescale website at http://freescale.com. follow worldwide web on- line instructions to retrieve the current mechanical specifications. advance information mc68hc908mr24 ? rev. 4.1 386 mechanical specifications freescale semiconductor mechanical specifications 22.3 64-pin plastic quad flat pack (qfp) figure 22-1. mc68hc908mr24fu 32 48 49 64 1 16 17 33 detail c -b- -a- -c- -d- -h- m b a c l s v g h e m l detail a k -h- u q r t w x detail c b b p -a-, -b-, d- detail a j f base metal d n section b-b ! "" # $ $ % # ! " " ! "" & "" ' ! ! $ ! ! ! "" ( ! ! $ ! % # % ! $ ! # ( ( ( ) ' ''( ''( ' ' ( ( ( '( ) ) '( # ' # ( ( ( ) ) ( ( # ' ' # ) ' ' ' mechanical specifications mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor mechanical specifications 387 22.4 56-pin shrink dual in-line package (sdip) figure 22-2. mc68hc908mr24b ?a? ?b? ?t? 56 29 128 seating plane j 56 pl d 56 pl s a m 0.25 (0.010) t n f g e s b m 0.25 (0.010) t k c h l m dim min max min max millimeters inches a 2.035 2.065 51.69 52.45 b 0.540 0.560 13.72 14.22 c 0.155 0.200 3.94 5.08 d 0.014 0.022 0.36 0.56 e 0.035 bsc 0.89 bsc f 0.032 0.046 0.81 1.17 g 0.070 bsc 1.778 bsc h 0.300 bsc 7.62 bsc j 0.008 0.015 0.20 0.38 k 0.115 0.135 2.92 3.43 l 0.600 bsc 15.24 bsc m 0 15 0 15 n 0.020 0.040 0.51 1.02 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of lead when formed parallel. 4. dimensions a and b do not include mold flash. maximum mold flash 0.25 (0.010) advance information mc68hc908mr24 ? rev. 4.1 388 mechanical specifications freescale semiconductor mechanical specifications mc68hc908mr24 ? rev. 4.1 advance information freescale semiconductor ordering information 389 advance information ? mc68hc908mr24 section 23. ordering information 23.1 contents 23.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 23.3 order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 23.2 introduction this section contains instructions for ordering the mc68hc908mr24. 23.3 order numbers table 23-1. order numbers mc order number (1) 1. fu = quad flat pack b = shrink dual in-line package operating temperature range 68hc908mr24cfu 68hc908mr24vfu ? 40 c to + 85 c ? 40 c to + 105 c 68hc908mr24cb 68hc908mr24vb ? 40 c to + 85 c ? 40 c to + 105 c advance information mc68hc908mr24 ? rev. 4.1 390 ordering information freescale semiconductor ordering information mc68hc908mr24 ? rev. 4.0 advance information motorola glossary 391 advance information ? mc68hc908mr24 glossary a ? see accumulator (a). accumulator (a) ? an 8-bit general-purpose r egister in the cpu08. the cpu08 uses the accumulator to hold operands and results of arithmetic and l ogic operations. acquisition mode ? a mode of pll op eration during star tup before the pll locks on a frequency. al so see tracking mode. address bus ? the set of wires that the cpu or dma uses to read and write memory locations. addressing mode ? the way that the c pu determines the operand address for an instruction. th e m68hc08 cpu has 16 addressing modes. alu ? see arithmetic logic unit (alu). arithmetic logic unit (alu) ? the portion of the cpu that contains the logic circuitry to perform arit hmetic, logic, and manipulation operations on operands. asynchronous ? refers to logic circuits and operations that are not synchronized by a co mmon reference signal. baud rate ? the total number of bits tr ansmitted per unit of time. bcd ? see binary-coded decimal (bcd). binary ? relating to the base 2 number system. binary-coded decimal (bcd) ? a notation that uses 4-bit binary numbers to represent the 10 decimal digits and th at retains the same positional structure of a dec imal number. for example, 234 (decimal) = 0010 0011 0100 (bcd) advance information mc68hc908mr24 ? rev. 4.0 392 glossary motorola glossary binary number system ? the base 2 number system, having two digits, 0 and 1. binary arithmetic is convenient in digital circuit design because digital circuits have two permissible voltage levels, low and high. the binary digits 0 and 1 ca n be interpreted to correspond to the two digital voltage levels. bit ? a binary digit. a bi t has a value of either logic 0 or logic 1. branch instruction ? an instructi on that causes t he cpu to continue processing at a memory locati on other than the next sequential address. break interrupt ? a software interrupt caused by the appearance on the internal address bus of the same value that is written in the break address registers. break module ? a module in the m68hc 08 family. the break module allows software to halt program execution at a programmable point to enter a ba ckground routine. breakpoint ? a number written into the break address registers of the break module. when a number appear s on the internal address bus that is the same as the number in the break address registers, the cpu executes the software interrupt instruction (swi). bus ? a set of wires that transfers logic signals. bus clocks ? there are two bus clo cks, it12 and it23. these clocks are generated by the cgm and dist ributed throughout the mcu by the sim. the frequency of the bus cl ocks, or operat ing frequency, is f op . while the frequency of these tw o clocks is the same, the phase is different. byte ? a set of eight bits. c ? the carry/borrow bit in the condition code re gister. the cpu08 sets the carry/borrow bit wh en an addition operation produces a carry out of bit 7 of the accumu lator or when a subtra ction operation requires a borrow. some logical operations and data manipulation instructions also clear or set the carry/borro w bit (as in bit test and branch instructions and sh ifts and rotates). ccr ? see condition code register. glossary mc68hc908mr24 ? rev. 4.0 advance information motorola glossary 393 central processor unit (cpu) ? the primary functi oning unit of any computer system. the cpu controls the execution of instructions. cgm ? see clock generat or module (cgm). clear ? to change a bit from logic 1 to logic 0; the opposite of set. clock ? a square wave signal used to synchronize events in a computer. clock generator module (cgm) ? a module in t he m68hc08 family. the cgm generates a base clock si gnal from which the system clocks are derived. the cgm may incl ude a crystal oscillator circuit and/or phase-locked loop (pll) circuit. comparator ? a device that compares th e magnitude of two inputs. a digital comparator defines the equality or relative differences between two binary numbers. computer operating pro perly module (cop) ? a counter module in the m68hc08 family that resets t he mcu if allow ed to overflow. condition code register (ccr) ? an 8-bit register in the cpu08 that contains the interrupt ma sk bit and five bits that indicate the results of the instruction just executed. control bit ? one bit of a regi ster manipulated by software to control the operation of the module. control unit ? one of two major units of the cpu. the control unit contains logic functions that syn chronize the machine and direct various operations. the control unit decodes instructions and generates the internal control si gnals that perform the requested operations. the outputs of the control unit driv e the execution unit, which contains the arithmetic logi c unit (alu), cpu registers, and bus interface. cop ? see computer operati ng properly module (cop). counter clock ? the input clock to the ti m counter. this clock is an output of the prescale r sub-module. the freque ncy of the counter clock is f tcnt , and the period is t tcnt . cpu ? see central pr ocessor unit (cpu). advance information mc68hc908mr24 ? rev. 4.0 394 glossary motorola glossary cpu08 ? the central processor unit of the m68hc08 family. cpu cycles ? a cpu clock cycle is one per iod of the internal bus-rate clock, f op , normally derived by dividing a crystal os cillator source by two or more so the high and low times wil l be equal. the length of time required to execut e an instruction is m easured in cpu clock cycles. cpu registers ? memory locations that ar e wired directly into the cpu logic instead of being part of the addressable memory map. the cpu always has direct access to the info rmation in these registers. the cpu registers in an m68hc08 are: a, 8-bit accumulator h:x, 16-bit index register sp, 16-bit stack pointer pc, 16-bit program counter ccr, condition code register containi ng the v, h, i, n, z, and c bits csic ? customer-specifi ed integrated circuit cycle time ? the period of the operating frequency: t cyc =1/f op . decimal number system ? base 10 numbering system that uses the digits zero through nine. direct memory access module (dma) ? an m68hc08 family module that can perform dat a transfers between any two cpu-addressable locations without cpu intervention. for transmitting or receiving blocks of data to or from peripherals, dma tran sfers are faster and more code-efficient than cpu interrupts. dma ? see direct memory access module (dma). dma service request ? a signal from a periphe ral to the dma module that enables the dma modu le to transfer data. duty cycle ? a ratio of the amount of time the signal is on versus the time it is off. duty cycle is us ually represented by a percentage. glossary mc68hc908mr24 ? rev. 4.0 advance information motorola glossary 395 eeprom ? electrically erasable, pr ogrammable, read-only memory. a non-volatile type of memory that can be electrically reprogrammed. eprom ? erasable, programmable, read -only memory. a non-volatile type of memory that can be erased by exposure to an ultraviolet light source and then reprogrammed. exception ? an event such as an interr upt or a reset that stops the sequential execution of the inst ructions in the main program. external interrupt module (irq) ? a module in th e m68hc08 family with both dedicated external interr upt pins and port pins that can be enabled as interrupt pins. fetch ? to copy data from a memory location into the accumulator. firmware ? instructions and data pr ogrammed into non-volatile memory. free-running counter ? a device that c ounts from zero to a predetermined number, t hen rolls over to zero and begins counting again. full-duplex transmission ? communication on a channel in which data can be sent and re ceived simultaneously. h ? the upper byte of the 16-bit index register (h:x) in the cpu08. h ? the half-carry bit in the condition code register of the cpu08. this bit indicates a carry from the low-or der four bits of the accumulator value to the high-order four bits . the half-carry bit is required for binary-coded decimal arithmetic operations. the decimal adjust accumulator (daa) instru ction uses the state of the h and c bits to determine the appropriate correction factor. hexadecimal ? base 16 numbering system that uses the digits 0 through 9 and the le tters a through f. high byte ? the most significant eight bits of a word. illegal address ? an address not with in the memory map. illegal opcode ? a non-existent opcode. advance information mc68hc908mr24 ? rev. 4.0 396 glossary motorola glossary i ? the interrupt mask bit in the condition code r egister of the cpu08. when i is set, all inte rrupts are disabled. index register (h:x) ? a 16-bit register in th e cpu08. the upper byte of h:x is called h. the lower byte is calle d x. in the indexed addressing modes, the cpu uses t he contents of h:x to determine the effective address of the oper and. h:x can also serve as a temporary data storage location. input/output (i/o) ? input/output interfac es between a computer system and the external world. a c pu reads an input to sense the level of an external si gnal and writes to an output to change the level on an external signal. instructions ? operations that a cpu can perform. instructions are expressed by programmers as assembly language mnemonics. a cpu interprets an opcode an d its associated operand(s) and instruction. interrupt ? a temporary break in the sequential exec ution of a program to respond to signals from peripheral devic es by executing a subroutine. interrupt request ? a signal from a peripheral to the cpu intended to cause the cpu to ex ecute a subroutine. i/o ? see input/output (i/0). irq ? see external in terrupt module (irq). jitter ? short-term si gnal instability. latch ? a circuit that retains the voltag e level (logic 1 or logic 0) written to it for as long as power is applied to the circuit. latency ? the time lag between inst ruction completion and data movement. least significant bit (lsb) ? the rightmost digi t of a binary number. logic 1 ? a voltage level approximately equal to the inpu t power voltage (v dd ). glossary mc68hc908mr24 ? rev. 4.0 advance information motorola glossary 397 logic 0 ? a voltage level approximatel y equal to t he ground voltage (v ss ). low byte ? the least significant eight bits of a word. low-voltage inhibi t module (lvi) ? a module in the m68hc08 family that monitors power supply voltage. lvi ? see low-voltage inhibit module (lvi). m68hc08 ? a freescale fami ly of 8-bit mcus. mark/space ? the logic 1/logic 0 convent ion used in formatting data in serial communication. mask ? 1. a logic circuit that forces a bit or group of bits to a desired state. 2. a photomask used in integr ated circuit fabrication to transfer an image onto silicon. mask option ? an optional micr ocontroller feature that the customer chooses to enabl e or disable. mask option register (mor) ? an eprom location c ontaining bits that enable or disable certain mcu features. mcu ? microcontroller unit. see microcontroller. memory location ? each m68hc08 memory location holds one byte of data and has a unique ad dress. to store info rmation in a memory location, the cpu places the addr ess of the location on the address bus, the data informat ion on the data bus, and asserts the write signal. to read information from a memory location, the cpu places the address of the location on the address bus and asserts the read signal. in response to the read signal, the sele cted memory location places its data onto the data bus. memory map ? a pictorial repres entation of all memo ry locations in a computer system. microcontroller ? microcontroller unit (m cu). a complete computer system, including a cpu, memo ry, a clock oscillator, and input/output (i/o) on a si ngle integrated circuit. advance information mc68hc908mr24 ? rev. 4.0 398 glossary motorola glossary modulo counter ? a counter that can be programmed to count to any number from zero to its maximum possible modulus. monitor rom ? a section of rom that can execute commands from a host computer for testing purposes. mor ? see mask option register (mor). most significant bit (msb) ? the leftmost digi t of a binary number. multiplexer ? a device that can select one of a number of inputs and pass the logic level of that input on to the output. n ? the negative bit in t he condition code regist er of the cpu08. the cpu sets the negative bit when an arithmet ic operation, logical operation, or data manipulati on produces a negative result. nibble ? a set of four bi ts (half of a byte). object code ? the output from an assembler or compiler that is itself executable machine code or is su itable for processing to produce executable machine code. opcode ? a binary code that instructs the cpu to perform an operation. open-drain ? an output that ha s no pullup transistor. an external pullup device can be connected to the power supply to provide the logic 1 output voltage. operand ? data on which an operation is perf ormed. usually, a statement consists of an operator and an operand. for example, the operator may be an add in struction, and the operand may be the quantity to be added. oscillator ? a circuit that produces a c onstant frequency square wave that is used by the computer as a timing and sequencing reference. otprom ? one-time programmable read- only memory. a non-volatile type of memory that cannot be reprogrammed. overflow ? a quantity that is too large to be contai ned in one byte or one word. page zero ? the first 256 bytes of me mory (addresses $0000?$00ff). glossary mc68hc908mr24 ? rev. 4.0 advance information motorola glossary 399 parity ? an error-checking scheme that counts the number of logic 1s in each byte transmitted. in a system that uses odd par ity, every byte is expected to have an odd number of logic 1s. in an even parity system, every byte should have an even number of logic 1s. in the transmitter, a parity gener ator appends an extra bi t to each byte to make the number of l ogic 1s odd for odd pa rity or even for even parity. a parity checker in the rece iver counts the number of logic 1s in each byte. the parity checker generat es an error signal if it finds a byte with an incorrec t number of logic 1s. pc ? see program counter (pc). peripheral ? a circuit not under direct cpu control. phase-locked loop (pll) ? an oscillator circui t in which the frequency of the oscillator is synchro nized to a re ference signal. pll ? see phase-locked loop (pll). pointer ? pointer register. an index register is sometimes called a pointer register because its contents are used in the calculation of the address of an operand and, theref ore, points to the operand. polarity ? the two opposite logic levels , logic 1 and logic 0, which correspond to two differ ent voltage levels, v dd and v ss . polling ? periodically reading a status bi t to monitor the condition of a peripheral device. port ? a set of wires for communi cating with off-chip devices. prescaler ? a circuit that generates an out put signal related to the input signal by a fractional scale factor such as 1/2, 1/8, 1/10, etc. program ? a set of computer instructions that ca uses a computer to perform a desired operat ion or operations. program counter (pc) ? a 16-bit register in the cpu08. the pc register holds the addre ss of the next instruct ion or operand that the cpu will use. pull ? an instruction that copies into the accumulator the contents of a stack ram location. the stack ram address is in the stack pointer. advance information mc68hc908mr24 ? rev. 4.0 400 glossary motorola glossary pullup ? a transistor in t he output of a logic ga te that connects the output to the logic 1 volt age of the power supply. pulse-width ? the amount of time a signal is on as opposed to being in its off state. pulse-width modulation (pwm) ? controlled variati on (modulation) of the pulse width of a signa l with a constant frequency. push ? an instruction that copies the contents of the accumulator to the stack ram. the stack ram addre ss is in the stack pointer. pwm period ? the time requir ed for one complete cycle of a pwm waveform. pmc ? pulse width modulated motor control module ram ? random access memory. all ra m locations ca n be read or written by the cpu. the contents of a ram memory location remain valid until the cpu writes a different value or until power is turned off. rc circuit ? a circuit consisting of c apacitors and resistors having a defined time constant. read ? to copy the contents of a memo ry location to the accumulator. register ? a circuit that st ores a group of bits. reserved memory location ? a memory location that is used only in special factory test modes. writ ing to a reserved location has no effect. reading a reserved locati on returns an unpredictable value. reset ? to force a device to a known condition. rom ? read-only memory. a type of memory that can be read but cannot be changed (written). the co ntents of rom must be specified before manufacturing the mcu. sci ? see serial communicati on interface module (sci). serial ? pertaining to sequential tr ansmission over a single line. serial communica tion interface module (sci) ? a module in the m68hc08 family that supports asynchronous communication. glossary mc68hc908mr24 ? rev. 4.0 advance information motorola glossary 401 serial peripheral inte rface module (spi) ? a module in the m68hc08 family that supports synchronous communicaton. set ? to change a bit from logic 0 to logic 1; opposi te of clear. shift register ? a chain of circuits that can retain the logic levels (logic 1 or logic 0) written to them and that can shift the logic levels to the right or left thr ough adjacent circui ts in the chain. signed ? a binary number not ation that accommodates both positive and negative numbers. the most significant bit is used to indicate whether the number is positive or negative, normal ly logic 0 for positive and logic 1 for negative. the other seven bits indicate the magnitude of the number. sim ? see system inte gration module (sim). software ? instructions and data that control the operation of a microcontroller. software interrupt (swi) ? an instruction that causes an interrupt and its associated vector fetch. spi ? see serial peripheral interface module (spi). stack ? a portion of ram reserved for st orage of cpu regi ster contents and subroutine return addresses. stack pointer (sp) ? a 16-bit register in the cpu08 containing the address of the next available storage location on the stack. start bit ? a bit that signals the beginni ng of an asynchronous serial transmission. status bit ? a register bit t hat indicates the c ondition of a device. stop bit ? a bit that signals the e nd of an asynchronous serial transmission. advance information mc68hc908mr24 ? rev. 4.0 402 glossary motorola glossary subroutine ? a sequence of instructions to be used more than once in the course of a progra m. the last instruction in a subroutine is a return from subroutine (rts) instru ction. at each pl ace in the main program where the subroutine ins tructions are needed, a jump or branch to subroutine (jsr or bsr) instruction is us ed to call the subroutine. the cpu leav es the flow of the ma in program to execute the instructions in the subroutin e. when the rts instruction is executed, the cpu return s to the main program where it left off. synchronous ? refers to logic circui ts and operations that are synchronized by a co mmon reference signal. system integration module (sim) ? one of a number of modules that handle a variety of contro l functions in the mo dular m68hc08 family. the sim controls mode of operation, resets and interrupts, and system clock distribution. tim ? see timer interface module (tim). timer interface module (tim) ? a module used to relate events in a system to a point in time. timer ? a module used to relate events in a system to a point in time. toggle ? to change the state of an output from a logic 0 to a logic 1 or from a logic 1 to a logic 0. tracking mode ? mode of low-jitter pll operation during which the pll is locked on a frequency. also see acquisition mode. two?s complement ? a means of performing binary subtraction using addition techniques. the most signific ant bit of a two?s complement number indicates the si gn of the number (1 indicates negative). the two?s complement negative of a numbe r is obtained by inverting each bit in the number and t hen adding 1 to the result. unbuffered ? utilizes only one register fo r data; new data overwrites current data. glossary mc68hc908mr24 ? rev. 4.0 advance information motorola glossary 403 unimplemented memory location ? a memory location that is not used. writing to an uni mplemented location has no effect. reading an unimplemented location re turns an unpredictable value. executing an opcode at an unimplem ented location caus es an illegal address reset. v ? the overflow bit in the condition code regi ster of the cpu08. the cpu08 sets the v bit w hen a two's complement overflow occurs. the signed branch instructions bgt, bge, ble, and blt use the overflow bit. variable ? a value that changes duri ng the course of program execution. vco ? see voltage-cont rolled oscillator. vector ? a memory location that cont ains the address of the beginning of a subroutine written to se rvice an interrupt or reset. voltage-controlled oscillator (vco) ? a circuit that produces an oscillating output signal of a frequ ency that is controlled by a dc voltage applied to a control input. waveform ? a graphical representation in which the amplitude of a wave is plotted against time. wired-or ? connection of circui t outputs so that if any output is high, the connection point is high. word ? a set of two bytes (16 bits). write ? the transfer of a byte of data from the cpu to a memory location. x ? the lower byte of the index register (h:x) in the cpu08. z ? the zero bit in the condition code register of the cpu08. the cpu08 sets the zero bit when an arithmetic operation, logical operation, or data manipulati on produces a result of $00. advance information mc68hc908mr24 ? rev. 4.0 404 glossary motorola glossary how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconduc tor@hibbertgroup.com information in this document is provid ed solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applic ations intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. the arm powered logo is a registered trademark of arm limited. arm7tdmi-s is a trademark of arm limited. java and all other java-based marks are trademarks or registered trademarks of sun microsystems, inc. in the u.s. and other countries. the bluetooth trademarks are owned by their proprietor and used by freescale semiconductor, inc. under license. ? freescale semiconductor, inc. 2005. all rights reserved. rev. 4.1 mc68hc908mr24/d august 1, 2005 |
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